diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
index a577ef23a..6772d7a71 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
+++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
@@ -162,9 +162,11 @@ struct acr_fw_header {
 
 /* ACR Falcon descriptor's */
 struct hs_acr {
-#define ACR_DEFAULT	0U
-#define ACR_AHESASC	1U
-#define ACR_ASB		2U
+#define ACR_DEFAULT		0U
+#define ACR_AHESASC_NON_FUSA	1U
+#define ACR_ASB_NON_FUSA	2U
+#define ACR_AHESASC_FUSA	3U
+#define ACR_ASB_FUSA		4U
 	u32 acr_type;
 
 	/* HS bootloader to validate & load ACR ucode */
diff --git a/drivers/gpu/nvgpu/common/acr/acr_priv.h b/drivers/gpu/nvgpu/common/acr/acr_priv.h
index edf2ff137..9f6b29a7d 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_priv.h
+++ b/drivers/gpu/nvgpu/common/acr/acr_priv.h
@@ -73,10 +73,15 @@ struct wpr_carveout_info;
 
 #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
 #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
-#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
-#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
-#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
-#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin"
+#define HSBIN_ACR_AHESASC_NON_FUSA_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
+#define HSBIN_ACR_ASB_NON_FUSA_PROD_UCODE "acr_asb_prod_ucode.bin"
+#define HSBIN_ACR_AHESASC_NON_FUSA_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
+#define HSBIN_ACR_ASB_NON_FUSA_DBG_UCODE "acr_asb_dbg_ucode.bin"
+
+#define HSBIN_ACR_AHESASC_FUSA_PROD_UCODE "acr_ahesasc_fusa_prod_ucode.bin"
+#define HSBIN_ACR_ASB_FUSA_PROD_UCODE "acr_asb_fusa_prod_ucode.bin"
+#define HSBIN_ACR_AHESASC_FUSA_DBG_UCODE "acr_ahesasc_fusa_dbg_ucode.bin"
+#define HSBIN_ACR_ASB_FUSA_DBG_UCODE "acr_asb_fusa_dbg_ucode.bin"
 
 #define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
 #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
diff --git a/drivers/gpu/nvgpu/common/acr/acr_sw_tu104.c b/drivers/gpu/nvgpu/common/acr/acr_sw_tu104.c
index d24ed1a48..62dc92748 100644
--- a/drivers/gpu/nvgpu/common/acr/acr_sw_tu104.c
+++ b/drivers/gpu/nvgpu/common/acr/acr_sw_tu104.c
@@ -70,20 +70,49 @@ static u32 tu104_acr_lsf_sec2(struct gk20a *g,
 	return BIT32(lsf->falcon_id);
 }
 
+/* fusa signing enable check */
+static bool tu104_acr_is_fusa_enabled(struct gk20a *g)
+{
+	return g->is_fusa_sku;
+}
+
 /* ACR-AHESASC(ACR hub encryption setter and signature checker) init*/
-static void nvgpu_tu104_acr_ahesasc_sw_init(struct gk20a *g,
+static void tu104_acr_ahesasc_non_fusa_ucode_select(struct gk20a *g,
+		struct hs_acr *acr_ahesasc)
+{
+	acr_ahesasc->acr_type = ACR_AHESASC_NON_FUSA;
+
+	if (!g->ops.pmu.is_debug_mode_enabled(g)) {
+		acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_NON_FUSA_PROD_UCODE;
+	} else {
+		acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_NON_FUSA_DBG_UCODE;
+	}
+
+}
+
+static void tu104_acr_ahesasc_fusa_ucode_select(struct gk20a *g,
+		struct hs_acr *acr_ahesasc)
+{
+	acr_ahesasc->acr_type = ACR_AHESASC_FUSA;
+
+	if (!g->ops.pmu.is_debug_mode_enabled(g)) {
+		acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_FUSA_PROD_UCODE;
+	} else {
+		acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_FUSA_DBG_UCODE;
+	}
+}
+
+static void tu104_acr_ahesasc_sw_init(struct gk20a *g,
 	struct hs_acr *acr_ahesasc)
 {
 	struct hs_flcn_bl *hs_bl = &acr_ahesasc->acr_hs_bl;
 
 	hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
 
-	acr_ahesasc->acr_type = ACR_AHESASC;
-
-	if (!g->ops.pmu.is_debug_mode_enabled(g)) {
-		acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_PROD_UCODE;
+	if (tu104_acr_is_fusa_enabled(g)) {
+		tu104_acr_ahesasc_fusa_ucode_select(g, acr_ahesasc);
 	} else {
-		acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_DBG_UCODE;
+		tu104_acr_ahesasc_non_fusa_ucode_select(g, acr_ahesasc);
 	}
 
 	acr_ahesasc->ptr_bl_dmem_desc = &acr_ahesasc->bl_dmem_desc_v1;
@@ -96,19 +125,41 @@ static void nvgpu_tu104_acr_ahesasc_sw_init(struct gk20a *g,
 }
 
 /* ACR-ASB(ACR SEC2 booter) init*/
-static void nvgpu_tu104_acr_asb_sw_init(struct gk20a *g,
+static void tu104_acr_asb_non_fusa_ucode_select(struct gk20a *g,
+	struct hs_acr *acr_asb)
+{
+	acr_asb->acr_type = ACR_ASB_NON_FUSA;
+
+	if (!g->ops.pmu.is_debug_mode_enabled(g)) {
+		acr_asb->acr_fw_name = HSBIN_ACR_ASB_NON_FUSA_PROD_UCODE;
+	} else {
+		acr_asb->acr_fw_name = HSBIN_ACR_ASB_NON_FUSA_DBG_UCODE;
+	}
+}
+
+static void tu104_acr_asb_fusa_ucode_select(struct gk20a *g,
+	struct hs_acr *acr_asb)
+{
+	acr_asb->acr_type = ACR_ASB_FUSA;
+
+	if (!g->ops.pmu.is_debug_mode_enabled(g)) {
+		acr_asb->acr_fw_name = HSBIN_ACR_ASB_FUSA_PROD_UCODE;
+	} else {
+		acr_asb->acr_fw_name = HSBIN_ACR_ASB_FUSA_DBG_UCODE;
+	}
+}
+
+static void tu104_acr_asb_sw_init(struct gk20a *g,
 	struct hs_acr *acr_asb)
 {
 	struct hs_flcn_bl *hs_bl = &acr_asb->acr_hs_bl;
 
 	hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
 
-	acr_asb->acr_type = ACR_ASB;
-
-	if (!g->ops.pmu.is_debug_mode_enabled(g)) {
-		acr_asb->acr_fw_name = HSBIN_ACR_ASB_PROD_UCODE;
+	if (tu104_acr_is_fusa_enabled(g)) {
+		tu104_acr_asb_fusa_ucode_select(g, acr_asb);
 	} else {
-		acr_asb->acr_fw_name = HSBIN_ACR_ASB_DBG_UCODE;
+		tu104_acr_asb_non_fusa_ucode_select(g, acr_asb);
 	}
 
 	acr_asb->ptr_bl_dmem_desc = &acr_asb->bl_dmem_desc_v1;
@@ -134,8 +185,8 @@ void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
 	acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr;
 
 	/* Init ACR-AHESASC */
-	nvgpu_tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc);
+	tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc);
 
 	/* Init ACR-ASB*/
-	nvgpu_tu104_acr_asb_sw_init(g, &acr->acr_asb);
+	tu104_acr_asb_sw_init(g, &acr->acr_asb);
 }