From 02e15b8a5e97c8f8a095715443d244b44e2753b5 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 9 May 2019 17:52:46 +0530 Subject: [PATCH] gpu: nvgpu: fix MISRA 10.3 violation in hal.gr.config unit Below MISRA 10.3 violation is reported in hal.gr.config unit Error: MISRA C-2012 Rule 10.3: nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:174: misra_violation: Implicit conversion of "pix_scale * min_scg_gpc_pix_perf + world_scale * scg_world_perf + tpc_scale * tpc_balance" from essential type "unsigned 32-bit int" to different or narrower essential type "signed 32-bit int". Fix this by declaring corresponding variables u32. This should have no functional impact as such Jira NVGPU-3406 Change-Id: I5b66c8db25c33afec3ab622a8d45997d5c8e6daa Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2115591 GVS: Gerrit_Virtual_Submit Reviewed-by: Philip Elcan Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c index 133c1e233..6c5cc0666 100644 --- a/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c +++ b/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c @@ -34,7 +34,7 @@ static int gr_gv100_scg_estimate_perf(struct gk20a *g, struct nvgpu_gr_config *gr_config, u32 *gpc_tpc_mask, u32 disable_gpc_id, u32 disable_tpc_id, - int *perf) + u32 *perf) { int err = 0; u32 scale_factor = 512U; /* Use fx23.9 */ @@ -186,7 +186,7 @@ int gv100_gr_config_init_sm_id_table(struct gk20a *g, u32 sm_id = 0; u32 sm_per_tpc = nvgpu_gr_config_get_sm_count_per_tpc(gr_config); u32 num_sm = sm_per_tpc * nvgpu_gr_config_get_tpc_count(gr_config); - int perf, maxperf; + u32 perf, maxperf; int err = 0; u32 *gpc_tpc_mask; u32 *tpc_table, *gpc_table; @@ -225,13 +225,13 @@ int gv100_gr_config_init_sm_id_table(struct gk20a *g, } for (gtpc = 0; gtpc < nvgpu_gr_config_get_tpc_count(gr_config); gtpc++) { - maxperf = -1; + maxperf = 0U; for (gpc = 0; gpc < nvgpu_gr_config_get_gpc_count(gr_config); gpc++) { gpc_tpc_mask_tmp = (unsigned long)gpc_tpc_mask[gpc]; for_each_set_bit(tpc_tmp, &gpc_tpc_mask_tmp, nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc)) { - perf = -1; + perf = 0U; tpc = (u32)tpc_tmp; err = gr_gv100_scg_estimate_perf(g, gr_config,