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gpu: nvgpu: fix misra violations in SDL

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The patch adds missing parentheses for macros used in SDL. It is required to
address the following misra violation: MISRA C-2012 Rule 20.7 - Macro parameter
expands into an expression without being wrapped by parentheses.

JIRA NVGPU-3180

Change-Id: I70d5359652c6e29814fe17e356dcd5553b498b34
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130260
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2019-06-04 15:09:58 +05:30
committed by mobile promotions
parent 591990212a
commit 0352bebc07
1 changed files with 109 additions and 109 deletions
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218
drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
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@@ -27,56 +27,56 @@
struct gk20a; struct gk20a;
#define NVGPU_ERR_MODULE_HOST 0U #define NVGPU_ERR_MODULE_HOST (0U)
#define NVGPU_ERR_MODULE_SM 1U #define NVGPU_ERR_MODULE_SM (1U)
#define NVGPU_ERR_MODULE_FECS 2U #define NVGPU_ERR_MODULE_FECS (2U)
#define NVGPU_ERR_MODULE_GPCCS 3U #define NVGPU_ERR_MODULE_GPCCS (3U)
#define NVGPU_ERR_MODULE_MMU 4U #define NVGPU_ERR_MODULE_MMU (4U)
#define NVGPU_ERR_MODULE_GCC 5U #define NVGPU_ERR_MODULE_GCC (5U)
#define NVGPU_ERR_MODULE_PMU 6U #define NVGPU_ERR_MODULE_PMU (6U)
#define NVGPU_ERR_MODULE_PGRAPH 7U #define NVGPU_ERR_MODULE_PGRAPH (7U)
#define NVGPU_ERR_MODULE_LTC 8U #define NVGPU_ERR_MODULE_LTC (8U)
#define NVGPU_ERR_MODULE_HUBMMU 9U #define NVGPU_ERR_MODULE_HUBMMU (9U)
#define NVGPU_ERR_MODULE_PRI 10U #define NVGPU_ERR_MODULE_PRI (10U)
#define NVGPU_ERR_MODULE_CE 11U #define NVGPU_ERR_MODULE_CE (11U)
#define GPU_HOST_PFIFO_BIND_ERROR 0U #define GPU_HOST_PFIFO_BIND_ERROR (0U)
#define GPU_HOST_PFIFO_SCHED_ERROR 1U #define GPU_HOST_PFIFO_SCHED_ERROR (1U)
#define GPU_HOST_PFIFO_CHSW_ERROR 2U #define GPU_HOST_PFIFO_CHSW_ERROR (2U)
#define GPU_HOST_PFIFO_MEMOP_TIMEOUT_ERROR 3U #define GPU_HOST_PFIFO_MEMOP_TIMEOUT_ERROR (3U)
#define GPU_HOST_PFIFO_LB_ERROR 4U #define GPU_HOST_PFIFO_LB_ERROR (4U)
#define GPU_HOST_PBUS_SQUASH_ERROR 5U #define GPU_HOST_PBUS_SQUASH_ERROR (5U)
#define GPU_HOST_PBUS_FECS_ERROR 6U #define GPU_HOST_PBUS_FECS_ERROR (6U)
#define GPU_HOST_PBUS_TIMEOUT_ERROR 7U #define GPU_HOST_PBUS_TIMEOUT_ERROR (7U)
#define GPU_HOST_PBDMA_TIMEOUT_ERROR 8U #define GPU_HOST_PBDMA_TIMEOUT_ERROR (8U)
#define GPU_HOST_PBDMA_EXTRA_ERROR 9U #define GPU_HOST_PBDMA_EXTRA_ERROR (9U)
#define GPU_HOST_PBDMA_GPFIFO_PB_ERROR 10U #define GPU_HOST_PBDMA_GPFIFO_PB_ERROR (10U)
#define GPU_HOST_PBDMA_METHOD_ERROR 11U #define GPU_HOST_PBDMA_METHOD_ERROR (11U)
#define GPU_HOST_PBDMA_SIGNATURE_ERROR 12U #define GPU_HOST_PBDMA_SIGNATURE_ERROR (12U)
#define GPU_HOST_PBDMA_HCE_ERROR 13U #define GPU_HOST_PBDMA_HCE_ERROR (13U)
#define GPU_HOST_PBDMA_PREEMPT_ERROR 14U #define GPU_HOST_PBDMA_PREEMPT_ERROR (14U)
#define GPU_HOST_PFIFO_CTXSW_TIMEOUT_ERROR 15U #define GPU_HOST_PFIFO_CTXSW_TIMEOUT_ERROR (15U)
#define GPU_HOST_INVALID_ERROR 16U #define GPU_HOST_INVALID_ERROR (16U)
#define GPU_SM_L1_TAG_ECC_CORRECTED 0U #define GPU_SM_L1_TAG_ECC_CORRECTED (0U)
#define GPU_SM_L1_TAG_ECC_UNCORRECTED 1U #define GPU_SM_L1_TAG_ECC_UNCORRECTED (1U)
#define GPU_SM_CBU_ECC_CORRECTED 2U #define GPU_SM_CBU_ECC_CORRECTED (2U)
#define GPU_SM_CBU_ECC_UNCORRECTED 3U #define GPU_SM_CBU_ECC_UNCORRECTED (3U)
#define GPU_SM_LRF_ECC_CORRECTED 4U #define GPU_SM_LRF_ECC_CORRECTED (4U)
#define GPU_SM_LRF_ECC_UNCORRECTED 5U #define GPU_SM_LRF_ECC_UNCORRECTED (5U)
#define GPU_SM_L1_DATA_ECC_CORRECTED 6U #define GPU_SM_L1_DATA_ECC_CORRECTED (6U)
#define GPU_SM_L1_DATA_ECC_UNCORRECTED 7U #define GPU_SM_L1_DATA_ECC_UNCORRECTED (7U)
#define GPU_SM_ICACHE_L0_DATA_ECC_CORRECTED 8U #define GPU_SM_ICACHE_L0_DATA_ECC_CORRECTED (8U)
#define GPU_SM_ICACHE_L0_DATA_ECC_UNCORRECTED 9U #define GPU_SM_ICACHE_L0_DATA_ECC_UNCORRECTED (9U)
#define GPU_SM_ICACHE_L1_DATA_ECC_CORRECTED 10U #define GPU_SM_ICACHE_L1_DATA_ECC_CORRECTED (10U)
#define GPU_SM_ICACHE_L1_DATA_ECC_UNCORRECTED 11U #define GPU_SM_ICACHE_L1_DATA_ECC_UNCORRECTED (11U)
#define GPU_SM_ICACHE_L0_PREDECODE_ECC_CORRECTED 12U #define GPU_SM_ICACHE_L0_PREDECODE_ECC_CORRECTED (12U)
#define GPU_SM_ICACHE_L0_PREDECODE_ECC_UNCORRECTED 13U #define GPU_SM_ICACHE_L0_PREDECODE_ECC_UNCORRECTED (13U)
#define GPU_SM_L1_TAG_MISS_FIFO_ECC_CORRECTED 14U #define GPU_SM_L1_TAG_MISS_FIFO_ECC_CORRECTED (14U)
#define GPU_SM_L1_TAG_MISS_FIFO_ECC_UNCORRECTED 15U #define GPU_SM_L1_TAG_MISS_FIFO_ECC_UNCORRECTED (15U)
#define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_CORRECTED 16U #define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_CORRECTED (16U)
#define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED 17U #define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED (17U)
#define GPU_SM_MACHINE_CHECK_ERROR 18U #define GPU_SM_MACHINE_CHECK_ERROR (18U)
struct gr_sm_mcerr_info { struct gr_sm_mcerr_info {
u64 hww_warp_esr_pc; /* PC which triggered the machine check error */ u64 hww_warp_esr_pc; /* PC which triggered the machine check error */
u32 hww_warp_esr_status;/* Error status register */ u32 hww_warp_esr_status;/* Error status register */
@@ -85,18 +85,18 @@ struct gr_sm_mcerr_info {
u32 tsgid; /* TSG to which the channel is bound */ u32 tsgid; /* TSG to which the channel is bound */
u32 tpc, gpc, sm; u32 tpc, gpc, sm;
}; };
#define GPU_SM_ICACHE_L1_PREDECODE_ECC_CORRECTED 19U #define GPU_SM_ICACHE_L1_PREDECODE_ECC_CORRECTED (19U)
#define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED 20U #define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED (20U)
#define GPU_FECS_FALCON_IMEM_ECC_CORRECTED 0U #define GPU_FECS_FALCON_IMEM_ECC_CORRECTED (0U)
#define GPU_FECS_FALCON_IMEM_ECC_UNCORRECTED 1U #define GPU_FECS_FALCON_IMEM_ECC_UNCORRECTED (1U)
#define GPU_FECS_FALCON_DMEM_ECC_CORRECTED 2U #define GPU_FECS_FALCON_DMEM_ECC_CORRECTED (2U)
#define GPU_FECS_FALCON_DMEM_ECC_UNCORRECTED 3U #define GPU_FECS_FALCON_DMEM_ECC_UNCORRECTED (3U)
#define GPU_FECS_CTXSW_WATCHDOG_TIMEOUT 4U #define GPU_FECS_CTXSW_WATCHDOG_TIMEOUT (4U)
#define GPU_FECS_CTXSW_CRC_MISMATCH 5U #define GPU_FECS_CTXSW_CRC_MISMATCH (5U)
#define GPU_FECS_FAULT_DURING_CTXSW 6U #define GPU_FECS_FAULT_DURING_CTXSW (6U)
#define GPU_FECS_CTXSW_INIT_ERROR 7U #define GPU_FECS_CTXSW_INIT_ERROR (7U)
#define GPU_FECS_INVALID_ERROR 8U #define GPU_FECS_INVALID_ERROR (8U)
struct ctxsw_err_info { struct ctxsw_err_info {
u32 curr_ctx; u32 curr_ctx;
u32 ctxsw_status0; u32 ctxsw_status0;
@@ -105,37 +105,37 @@ struct ctxsw_err_info {
u32 mailbox_value; u32 mailbox_value;
}; };
#define GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED 0U #define GPU_GPCCS_FALCON_IMEM_ECC_CORRECTED (0U)
#define GPU_GPCCS_FALCON_IMEM_ECC_UNCORRECTED 1U #define GPU_GPCCS_FALCON_IMEM_ECC_UNCORRECTED (1U)
#define GPU_GPCCS_FALCON_DMEM_ECC_CORRECTED 2U #define GPU_GPCCS_FALCON_DMEM_ECC_CORRECTED (2U)
#define GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED 3U #define GPU_GPCCS_FALCON_DMEM_ECC_UNCORRECTED (3U)
#define GPU_MMU_L1TLB_ECC_CORRECTED 0U #define GPU_MMU_L1TLB_ECC_CORRECTED (0U)
#define GPU_MMU_L1TLB_ECC_UNCORRECTED 1U #define GPU_MMU_L1TLB_ECC_UNCORRECTED (1U)
#define GPU_MMU_L1TLB_SA_DATA_ECC_CORRECTED 2U #define GPU_MMU_L1TLB_SA_DATA_ECC_CORRECTED (2U)
#define GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED 3U #define GPU_MMU_L1TLB_SA_DATA_ECC_UNCORRECTED (3U)
#define GPU_MMU_L1TLB_FA_DATA_ECC_CORRECTED 4U #define GPU_MMU_L1TLB_FA_DATA_ECC_CORRECTED (4U)
#define GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED 5U #define GPU_MMU_L1TLB_FA_DATA_ECC_UNCORRECTED (5U)
#define GPU_GCC_L15_ECC_CORRECTED 0U #define GPU_GCC_L15_ECC_CORRECTED (0U)
#define GPU_GCC_L15_ECC_UNCORRECTED 1U #define GPU_GCC_L15_ECC_UNCORRECTED (1U)
#define GPU_PMU_FALCON_IMEM_ECC_CORRECTED 0U #define GPU_PMU_FALCON_IMEM_ECC_CORRECTED (0U)
#define GPU_PMU_FALCON_IMEM_ECC_UNCORRECTED 1U #define GPU_PMU_FALCON_IMEM_ECC_UNCORRECTED (1U)
#define GPU_PMU_FALCON_DMEM_ECC_CORRECTED 2U #define GPU_PMU_FALCON_DMEM_ECC_CORRECTED (2U)
#define GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED 3U #define GPU_PMU_FALCON_DMEM_ECC_UNCORRECTED (3U)
#define GPU_PMU_BAR0_ERROR_TIMEOUT 4U #define GPU_PMU_BAR0_ERROR_TIMEOUT (4U)
#define GPU_PGRAPH_FE_EXCEPTION 0U #define GPU_PGRAPH_FE_EXCEPTION (0U)
#define GPU_PGRAPH_MEMFMT_EXCEPTION 1U #define GPU_PGRAPH_MEMFMT_EXCEPTION (1U)
#define GPU_PGRAPH_PD_EXCEPTION 2U #define GPU_PGRAPH_PD_EXCEPTION (2U)
#define GPU_PGRAPH_SCC_EXCEPTION 3U #define GPU_PGRAPH_SCC_EXCEPTION (3U)
#define GPU_PGRAPH_DS_EXCEPTION 4U #define GPU_PGRAPH_DS_EXCEPTION (4U)
#define GPU_PGRAPH_SSYNC_EXCEPTION 5U #define GPU_PGRAPH_SSYNC_EXCEPTION (5U)
#define GPU_PGRAPH_MME_EXCEPTION 6U #define GPU_PGRAPH_MME_EXCEPTION (6U)
#define GPU_PGRAPH_SKED_EXCEPTION 7U #define GPU_PGRAPH_SKED_EXCEPTION (7U)
#define GPU_PGRAPH_BE_EXCEPTION 8U #define GPU_PGRAPH_BE_EXCEPTION (8U)
#define GPU_PGRAPH_MPC_EXCEPTION 9U #define GPU_PGRAPH_MPC_EXCEPTION (9U)
struct gr_exception_info { struct gr_exception_info {
u32 curr_ctx; /* Context which triggered the exception */ u32 curr_ctx; /* Context which triggered the exception */
u32 chid; /* Channel bound to the context */ u32 chid; /* Channel bound to the context */
@@ -143,32 +143,32 @@ struct gr_exception_info {
u32 status; /* Exception status */ u32 status; /* Exception status */
}; };
#define GPU_LTC_CACHE_DSTG_ECC_CORRECTED 0U #define GPU_LTC_CACHE_DSTG_ECC_CORRECTED (0U)
#define GPU_LTC_CACHE_DSTG_ECC_UNCORRECTED 1U #define GPU_LTC_CACHE_DSTG_ECC_UNCORRECTED (1U)
#define GPU_LTC_CACHE_TSTG_ECC_CORRECTED 2U #define GPU_LTC_CACHE_TSTG_ECC_CORRECTED (2U)
#define GPU_LTC_CACHE_TSTG_ECC_UNCORRECTED 3U #define GPU_LTC_CACHE_TSTG_ECC_UNCORRECTED (3U)
#define GPU_LTC_CACHE_RSTG_ECC_CORRECTED 4U #define GPU_LTC_CACHE_RSTG_ECC_CORRECTED (4U)
#define GPU_LTC_CACHE_RSTG_ECC_UNCORRECTED 5U #define GPU_LTC_CACHE_RSTG_ECC_UNCORRECTED (5U)
#define GPU_LTC_CACHE_DSTG_BE_ECC_CORRECTED 6U #define GPU_LTC_CACHE_DSTG_BE_ECC_CORRECTED (6U)
#define GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED 7U #define GPU_LTC_CACHE_DSTG_BE_ECC_UNCORRECTED (7U)
#define GPU_HUBMMU_L2TLB_SA_DATA_ECC_CORRECTED 0U #define GPU_HUBMMU_L2TLB_SA_DATA_ECC_CORRECTED (0U)
#define GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED 1U #define GPU_HUBMMU_L2TLB_SA_DATA_ECC_UNCORRECTED (1U)
#define GPU_HUBMMU_TLB_SA_DATA_ECC_CORRECTED 2U #define GPU_HUBMMU_TLB_SA_DATA_ECC_CORRECTED (2U)
#define GPU_HUBMMU_TLB_SA_DATA_ECC_UNCORRECTED 3U #define GPU_HUBMMU_TLB_SA_DATA_ECC_UNCORRECTED (3U)
#define GPU_HUBMMU_PTE_DATA_ECC_CORRECTED 4U #define GPU_HUBMMU_PTE_DATA_ECC_CORRECTED (4U)
#define GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED 5U #define GPU_HUBMMU_PTE_DATA_ECC_UNCORRECTED (5U)
#define GPU_HUBMMU_PDE0_DATA_ECC_CORRECTED 6U #define GPU_HUBMMU_PDE0_DATA_ECC_CORRECTED (6U)
#define GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED 7U #define GPU_HUBMMU_PDE0_DATA_ECC_UNCORRECTED (7U)
#define GPU_PRI_TIMEOUT_ERROR 0U #define GPU_PRI_TIMEOUT_ERROR (0U)
#define GPU_PRI_ACCESS_VIOLATION 1U #define GPU_PRI_ACCESS_VIOLATION (1U)
#define GPU_CE_LAUNCH_ERROR 0U #define GPU_CE_LAUNCH_ERROR (0U)
#define GPU_CE_BLOCK_PIPE 1U #define GPU_CE_BLOCK_PIPE (1U)
#define GPU_CE_NONBLOCK_PIPE 2U #define GPU_CE_NONBLOCK_PIPE (2U)
#define GPU_CE_INVALID_CONFIG 3U #define GPU_CE_INVALID_CONFIG (3U)
#define GPU_CE_METHOD_BUFFER_FAULT 4U #define GPU_CE_METHOD_BUFFER_FAULT (4U)
struct gr_err_info { struct gr_err_info {
struct gr_sm_mcerr_info *sm_mcerr_info; struct gr_sm_mcerr_info *sm_mcerr_info;