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gpu: nvgpu: gr/init MISRA fix for Rule 14.3

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Fix MISRA error for Rule 14.3
The switch governing value "offset" cannot reach the default case.
Execution cannot reach this statement "default:".

Change switch statement with if else checking

Jira NVGPU-3227

Change-Id: Ib1ccfe2d3bef94ffaf3e0f963bc21260844d0c91
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110759
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-05-02 17:39:05 -07:00
committed by mobile promotions
parent b06d43e715
commit 03c6929f69
1 changed files with 7 additions and 15 deletions
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22
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
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@@ -489,29 +489,21 @@ int gv11b_gr_init_rop_mapping(struct gk20a *g,
&& (num_tpcs > 0U)) { && (num_tpcs > 0U)) {
tile_cnt = nvgpu_gr_config_get_map_tile_count( tile_cnt = nvgpu_gr_config_get_map_tile_count(
gr_config, base + offset); gr_config, base + offset);
switch (offset) { if (offset == 0U) {
case 0:
map = map | gr_crstr_gpc_map_tile0_f(tile_cnt); map = map | gr_crstr_gpc_map_tile0_f(tile_cnt);
break; } else if (offset == 1U) {
case 1:
map = map | gr_crstr_gpc_map_tile1_f(tile_cnt); map = map | gr_crstr_gpc_map_tile1_f(tile_cnt);
break; } else if (offset == 2U) {
case 2:
map = map | gr_crstr_gpc_map_tile2_f(tile_cnt); map = map | gr_crstr_gpc_map_tile2_f(tile_cnt);
break; } else if (offset == 3U) {
case 3:
map = map | gr_crstr_gpc_map_tile3_f(tile_cnt); map = map | gr_crstr_gpc_map_tile3_f(tile_cnt);
break; } else if (offset == 4U) {
case 4:
map = map | gr_crstr_gpc_map_tile4_f(tile_cnt); map = map | gr_crstr_gpc_map_tile4_f(tile_cnt);
break; } else if (offset == 5U) {
case 5:
map = map | gr_crstr_gpc_map_tile5_f(tile_cnt); map = map | gr_crstr_gpc_map_tile5_f(tile_cnt);
break; } else {
default:
nvgpu_err(g, "incorrect rop mapping %x", nvgpu_err(g, "incorrect rop mapping %x",
offset); offset);
break;
} }
num_tpcs--; num_tpcs--;
offset++; offset++;