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gpu: nvgpu: fix MISRA 17.7 in nvgpu.common.hal.fifo.*

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MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.common.hal.fifo.runlist
- nvgpu.common.hal.fifo.fifo

JIRA NVGPU-3039

Change-Id: I9483f5cb623cfe36d6b26e41c33f124c24710c08
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098765
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Nicolas Benech
2019-04-16 10:53:29 -04:00
committed by mobile promotions
parent 9449396ffc
commit 0435ca4eb3
4 changed files with 44 additions and 7 deletions
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9
drivers/gpu/nvgpu/hal/rc/rc_gk20a.c
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@@ -118,8 +118,13 @@ void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 eng_bitmask,
g->ops.fifo.intr_set_recover_mask(g);
g->ops.fifo.trigger_mmu_fault(g, engine_ids);
gk20a_fifo_handle_mmu_fault_locked(g, mmu_fault_engines, ref_id,
ref_id_is_tsg);
/*
* Ignore the "Verbose" flag from
* gk20a_fifo_handle_mmu_fault_locked since it is not needed
* here
*/
(void) gk20a_fifo_handle_mmu_fault_locked(g, mmu_fault_engines,
ref_id, ref_id_is_tsg);
g->ops.fifo.intr_unset_recover_mask(g);
}