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gpu: nvgpu: fix MISRA Rule 10.3 and 10.4 violations

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BVEC changes for nvgpu_rc_pbdma_fault and nvgpu_rc_mmu_fault
started reporting below MISRA issue.

kernel/nvgpu/drivers/gpu/nvgpu/common/fifo/tsg.c:522:
  1. misra_c_2012_rule_10_4_violation: Essential type of the left hand
     operand "error_notifier" (unsigned) is not the same as that of
     the right operand "NVGPU_ERR_NOTIFIER_INVAL"(enum).

kernel/nvgpu/drivers/gpu/nvgpu/common/fifo/tsg.c:541:
  1. misra_c_2012_rule_10_3_violation: Implicit conversion of
     "NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT" from essential type
     "anonymous enum" to different or narrower essential type
     "unsigned 32-bit int".

Change the enum nvgpu_err_notif values to u32 values declared using
the #define macro.

JIRA NVGPU-6772

Change-Id: Icac7f567cea52cde07ca200b21eb3e7dd2b9e645
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2584153
(cherry picked from commit 2f073f341bd55242c857c6c6d35d6015495025e2)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623634
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kamble
2021-08-27 10:42:05 +05:30
committed by mobile promotions
parent bcbccbe083
commit 04587333ca
3 changed files with 15 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/rc/rc.c
View File

@@ -95,7 +95,7 @@ void nvgpu_rc_ctxsw_timeout(struct gk20a *g, u32 eng_bitmask,
#endif
}
int nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, enum nvgpu_err_notif error_notifier,
int nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, u32 error_notifier,
struct nvgpu_pbdma_status_info *pbdma_status)
{
u32 id_type = PBDMA_STATUS_ID_TYPE_INVALID;

28
drivers/gpu/nvgpu/include/nvgpu/error_notifier.h
View File

@@ -27,21 +27,19 @@
struct nvgpu_channel;
enum nvgpu_err_notif {
NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT = 0,
NVGPU_ERR_NOTIFIER_GR_ERROR_SW_METHOD,
NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY,
NVGPU_ERR_NOTIFIER_GR_EXCEPTION,
NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT,
NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY,
NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT,
NVGPU_ERR_NOTIFIER_PBDMA_ERROR,
NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD,
NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR,
NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH,
NVGPU_ERR_NOTIFIER_CE_ERROR,
NVGPU_ERR_NOTIFIER_INVAL,
};
#define NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT 0U
#define NVGPU_ERR_NOTIFIER_GR_ERROR_SW_METHOD 1U
#define NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY 2U
#define NVGPU_ERR_NOTIFIER_GR_EXCEPTION 3U
#define NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT 4U
#define NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY 5U
#define NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT 6U
#define NVGPU_ERR_NOTIFIER_PBDMA_ERROR 7U
#define NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD 8U
#define NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR 9U
#define NVGPU_ERR_NOTIFIER_PBDMA_PUSHBUFFER_CRC_MISMATCH 10U
#define NVGPU_ERR_NOTIFIER_CE_ERROR 11U
#define NVGPU_ERR_NOTIFIER_INVAL 12U
void nvgpu_set_err_notifier_locked(struct nvgpu_channel *ch, u32 error);
void nvgpu_set_err_notifier(struct nvgpu_channel *ch, u32 error);

3
drivers/gpu/nvgpu/include/nvgpu/rc.h
View File

@@ -103,7 +103,6 @@ struct nvgpu_tsg;
struct nvgpu_channel;
struct nvgpu_pbdma_status_info;
struct mmu_fault_info;
enum nvgpu_err_notif;
static inline const char *nvgpu_rc_type_to_str(unsigned int rc_type)
{
@@ -182,7 +181,7 @@ void nvgpu_rc_ctxsw_timeout(struct gk20a *g, u32 eng_bitmask,
* 4. the channel is not bound to tsg.
* 5. the id type or next_id type are not indicating channel id type or tsg id type.
*/
int nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, enum nvgpu_err_notif error_notifier,
int nvgpu_rc_pbdma_fault(struct gk20a *g, u32 pbdma_id, u32 error_notifier,
struct nvgpu_pbdma_status_info *pbdma_status);
/**