From 04786d1a2e4874da267e7dc368d1741ee1411234 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 13 Mar 2019 19:34:00 +0530 Subject: [PATCH] gpu: nvgpu: add hal.gr.init hal to enable/disable fe_go_idle timeout Add new hal operation g->ops.gr.init.fe_go_idle_timeout() in hal.gr.init unit to enable/disable fe_go_idle timeout Use this hal in gr_gk20a_init_golden_ctx_image() instead of direct register access Remove timeout disable/enable code in gk20a_init_sw_bundle() since parent API gr_gk20a_init_golden_ctx_image() is already taking care of that Jira NVGPU-2961 Change-Id: Ice72699059f031ca0b1994fa57661716a6c66cd2 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2072550 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 17 ++--------------- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 11 ++++++----- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 11 ++++++----- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c | 11 +++++++++++ drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 ++ drivers/gpu/nvgpu/tu104/hal_tu104.c | 1 + 9 files changed, 31 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 7cf5865ec..d19937c13 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -998,9 +998,6 @@ int gk20a_init_sw_bundle(struct gk20a *g) int err = 0; unsigned int i; - /* disable fe_go_idle */ - gk20a_writel(g, gr_fe_go_idle_timeout_r(), - gr_fe_go_idle_timeout_count_disabled_f()); /* enable pipe mode override */ gk20a_writel(g, gr_pipe_bundle_config_r(), gr_pipe_bundle_config_override_pipe_mode_enabled_f()); @@ -1050,10 +1047,6 @@ int gk20a_init_sw_bundle(struct gk20a *g) err = g->ops.gr.init.wait_idle(g); - /* restore fe_go_idle */ - gk20a_writel(g, gr_fe_go_idle_timeout_r(), - gr_fe_go_idle_timeout_count_prod_f()); - return err; error: @@ -1061,10 +1054,6 @@ error: gk20a_writel(g, gr_pipe_bundle_config_r(), gr_pipe_bundle_config_override_pipe_mode_disabled_f()); - /* restore fe_go_idle */ - gk20a_writel(g, gr_fe_go_idle_timeout_r(), - gr_fe_go_idle_timeout_count_prod_f()); - return err; } @@ -1137,8 +1126,7 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g, } /* disable fe_go_idle */ - gk20a_writel(g, gr_fe_go_idle_timeout_r(), - gr_fe_go_idle_timeout_count_disabled_f()); + g->ops.gr.init.fe_go_idle_timeout(g, false); err = g->ops.gr.commit_global_ctx_buffers(g, gr_ctx, false); if (err != 0) { @@ -1166,8 +1154,7 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g, restore_fe_go_idle: /* restore fe_go_idle */ - gk20a_writel(g, gr_fe_go_idle_timeout_r(), - gr_fe_go_idle_timeout_count_prod_f()); + g->ops.gr.init.fe_go_idle_timeout(g, true); if ((err != 0) || (g->ops.gr.init.wait_idle(g) != 0)) { goto clean_up; diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 17d93be44..44ff1c8e3 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -424,15 +424,16 @@ static const struct gpu_ops gm20b_ops = { .get_gpcs_swdx_dss_zbc_z_format_reg = NULL, }, .init = { + .pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc, + .pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc, + .cwd_gpcs_tpcs_num = gm20b_gr_init_cwd_gpcs_tpcs_num, + .wait_idle = gm20b_gr_init_wait_idle, + .wait_fe_idle = gm20b_gr_init_wait_fe_idle, .fe_pwr_mode_force_on = gm20b_gr_init_fe_pwr_mode_force_on, .override_context_reset = gm20b_gr_init_override_context_reset, - .wait_idle = gm20b_gr_init_wait_idle, - .wait_fe_idle = gm20b_gr_init_wait_fe_idle, - .pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc, - .pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc, - .cwd_gpcs_tpcs_num = gm20b_gr_init_cwd_gpcs_tpcs_num, + .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, }, }, .fb = { diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 217db9ca3..ee39af885 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -505,6 +505,7 @@ static const struct gpu_ops gp10b_ops = { .override_context_reset = gm20b_gr_init_override_context_reset, .preemption_state = gp10b_gr_init_preemption_state, + .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, }, }, .fb = { diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index b6d9f03c9..0059ba3bc 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -629,15 +629,16 @@ static const struct gpu_ops gv100_ops = { gv100_gr_hwpm_map_get_active_fbpa_mask, }, .init = { + .pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc, + .pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc, + .cwd_gpcs_tpcs_num = gm20b_gr_init_cwd_gpcs_tpcs_num, + .wait_idle = gm20b_gr_init_wait_idle, + .wait_fe_idle = gm20b_gr_init_wait_fe_idle, .fe_pwr_mode_force_on = gm20b_gr_init_fe_pwr_mode_force_on, .override_context_reset = gm20b_gr_init_override_context_reset, - .wait_idle = gm20b_gr_init_wait_idle, - .wait_fe_idle = gm20b_gr_init_wait_fe_idle, - .pd_tpc_per_gpc = gm20b_gr_init_pd_tpc_per_gpc, - .pd_skip_table_gpc = gm20b_gr_init_pd_skip_table_gpc, - .cwd_gpcs_tpcs_num = gm20b_gr_init_cwd_gpcs_tpcs_num, + .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, }, }, .fb = { diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0c7eee4ec..1a325c3db 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -598,6 +598,7 @@ static const struct gpu_ops gv11b_ops = { .override_context_reset = gm20b_gr_init_override_context_reset, .preemption_state = gv11b_gr_init_preemption_state, + .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, }, }, .fb = { diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c index 0bfa98913..a8f0b8214 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c @@ -269,3 +269,14 @@ void gm20b_gr_init_override_context_reset(struct gk20a *g) nvgpu_udelay(FECS_CTXSW_RESET_DELAY_US); (void) nvgpu_readl(g, gr_fecs_ctxsw_reset_ctl_r()); } + +void gm20b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable) +{ + if (enable) { + nvgpu_writel(g, gr_fe_go_idle_timeout_r(), + gr_fe_go_idle_timeout_count_prod_f()); + } else { + nvgpu_writel(g, gr_fe_go_idle_timeout_r(), + gr_fe_go_idle_timeout_count_disabled_f()); + } +} diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h index 7c402dc15..cbc57ce68 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h @@ -35,5 +35,6 @@ int gm20b_gr_init_wait_idle(struct gk20a *g); int gm20b_gr_init_wait_fe_idle(struct gk20a *g); int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on); void gm20b_gr_init_override_context_reset(struct gk20a *g); +void gm20b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable); #endif /* NVGPU_GR_INIT_GM20B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index f297c80c6..3e3f7c978 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -684,6 +684,8 @@ struct gpu_ops { int (*preemption_state)(struct gk20a *g, u32 gfxp_wfi_timeout_count, bool gfxp_wfi_timeout_unit_usec); + void (*fe_go_idle_timeout)(struct gk20a *g, + bool enable); } init; u32 (*fecs_falcon_base_addr)(void); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index aec810ade..2da2526bc 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -666,6 +666,7 @@ static const struct gpu_ops tu104_ops = { .override_context_reset = gm20b_gr_init_override_context_reset, .preemption_state = gv11b_gr_init_preemption_state, + .fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout, }, }, .fb = {