diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 99f1db2eb..4143f18c8 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -25,6 +25,7 @@ #include "hal/fifo/engines_gm20b.h" #include "hal/fifo/pbdma_gm20b.h" #include "hal/fifo/pbdma_gp10b.h" +#include "hal/fifo/ramin_gk20a.h" #include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/ramin_gp10b.h" #include "hal/fifo/userd_gk20a.h" @@ -506,6 +507,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .set_gr_ptr = NULL, .set_big_page_size = gm20b_ramin_set_big_page_size, .init_pdb = gp10b_ramin_init_pdb, + .set_adr_limit = gk20a_ramin_set_adr_limit, }, .runlist = { .reschedule = NULL, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 110f938a1..d5c68333b 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -595,6 +595,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .set_gr_ptr = NULL, .set_big_page_size = gm20b_ramin_set_big_page_size, .init_pdb = gp10b_ramin_init_pdb, + .set_adr_limit = NULL, }, .runlist = { .reschedule = NULL, diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index a4c65b62f..561523722 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -384,11 +384,7 @@ void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem); - nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_lo_w(), - u64_lo32(vm->va_limit - 1U) & ~0xfffU); - - nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_hi_w(), - ram_in_adr_limit_hi_f(u64_hi32(vm->va_limit - 1U))); + g->ops.ramin.set_adr_limit(g, inst_block, vm->va_limit - 1U); if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) { g->ops.ramin.set_big_page_size(g, inst_block, big_page_size); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 67782f313..76fa49974 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -700,6 +700,7 @@ static const struct gpu_ops gm20b_ops = { .set_gr_ptr = gk20a_ramin_set_gr_ptr, .set_big_page_size = gm20b_ramin_set_big_page_size, .init_pdb = gk20a_ramin_init_pdb, + .set_adr_limit = gk20a_ramin_set_adr_limit, }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 2dbfe403a..ae19331de 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -788,6 +788,7 @@ static const struct gpu_ops gp10b_ops = { .set_gr_ptr = gk20a_ramin_set_gr_ptr, .set_big_page_size = gm20b_ramin_set_big_page_size, .init_pdb = gp10b_ramin_init_pdb, + .set_adr_limit = gk20a_ramin_set_adr_limit, }, .runlist = { .reschedule = gk20a_runlist_reschedule, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 62ae7fc01..d60445ff5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -973,6 +973,7 @@ static const struct gpu_ops gv100_ops = { .set_gr_ptr = gv11b_ramin_set_gr_ptr, .set_big_page_size = gm20b_ramin_set_big_page_size, .init_pdb = gp10b_ramin_init_pdb, + .set_adr_limit = NULL, }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 810dfda13..c5c1dab15 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -928,6 +928,7 @@ static const struct gpu_ops gv11b_ops = { .set_gr_ptr = gv11b_ramin_set_gr_ptr, .set_big_page_size = gm20b_ramin_set_big_page_size, .init_pdb = gp10b_ramin_init_pdb, + .set_adr_limit = NULL, }, .runlist = { .reschedule = gv11b_runlist_reschedule, diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c index 2c6193e6e..77ab3d5a3 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c @@ -63,3 +63,12 @@ void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, ram_in_page_dir_base_hi_f(pdb_addr_hi)); } +void gk20a_ramin_set_adr_limit(struct gk20a *g, + struct nvgpu_mem *inst_block, u64 va_limit) +{ + nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_lo_w(), + u64_lo32(va_limit - 1U) & ~0xfffU); + + nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_hi_w(), + ram_in_adr_limit_hi_f(u64_hi32(va_limit - 1U))); +} diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h index 877b8bf07..b065a1267 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h @@ -31,5 +31,7 @@ void gk20a_ramin_set_gr_ptr(struct gk20a *g, struct nvgpu_mem *inst_block, u64 gpu_va); void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, u64 pdb_addr, struct nvgpu_mem *pdb_mem); +void gk20a_ramin_set_adr_limit(struct gk20a *g, + struct nvgpu_mem *inst_block, u64 va_limit); #endif /* NVGPU_RAMIN_GK20A_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 3880be43a..27f3608b0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1024,6 +1024,8 @@ struct gpu_ops { struct nvgpu_mem *mem, u32 size); void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block, u64 pdb_addr, struct nvgpu_mem *pdb_mem); + void (*set_adr_limit)(struct gk20a *g, + struct nvgpu_mem *inst_block, u64 va_limit); } ramin; struct { int (*reschedule)(struct channel_gk20a *ch, bool preempt_next); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 4819206ce..04610fe62 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -1011,6 +1011,7 @@ static const struct gpu_ops tu104_ops = { .set_gr_ptr = gv11b_ramin_set_gr_ptr, .set_big_page_size = gm20b_ramin_set_big_page_size, .init_pdb = gp10b_ramin_init_pdb, + .set_adr_limit = NULL, }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel,