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gpu: nvgpu: re-arrange parity counters
(1) Re-arrange the structure for parity counters reporting so multiple units can be managed JIRA: GPUT19X-84 Change-Id: If59a883dfe22d5a1d91a6d0ed2f5a6254434ffcb Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1485276 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -29,6 +29,7 @@ struct gk20a_ctxsw_trace;
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struct acr_desc;
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struct nvgpu_mem_alloc_tracker;
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struct dbg_profiler_object_data;
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struct ecc_gk20a;
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#include <linux/sched.h>
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#include <nvgpu/lock.h>
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@@ -69,6 +70,7 @@ struct dbg_profiler_object_data;
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#include "pmgr/pmgr.h"
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#include "therm/thrm.h"
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#endif
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#include "ecc_gk20a.h"
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#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)
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#define WRITE_ONCE(x, val) \
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@@ -991,6 +993,7 @@ struct gk20a {
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struct mm_gk20a mm;
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struct pmu_gk20a pmu;
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struct acr_desc acr;
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struct ecc_gk20a ecc;
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struct cooling_device_gk20a gk20a_cdev;
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#ifdef CONFIG_ARCH_TEGRA_18x_SOC
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struct clk_pmupstate clk_pmu;
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