diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 097be6681..6c8f6c5ca 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -55,9 +55,6 @@ struct perf_pmupstate;
 struct vin_device_v20;
 struct avfsvinobjs;
 struct set_fll_clk;
-struct boardobjgrp;
-struct boardobjgrp_pmu_cmd;
-struct boardobjgrpmask;
 
 #include <nvgpu/lock.h>
 #include <nvgpu/thread.h>
@@ -82,6 +79,7 @@ struct boardobjgrpmask;
 #include "gk20a/clk_gk20a.h"
 #include "gk20a/fifo_gk20a.h"
 #include "gk20a/gr_gk20a.h"
+#include "pmgr/pmgr.h"
 
 #ifdef CONFIG_DEBUG_FS
 struct railgate_stats {
@@ -1496,7 +1494,7 @@ struct gk20a {
 	struct nvgpu_ecc ecc;
 	struct clk_pmupstate *clk_pmu;
 	struct perf_pmupstate *perf_pmu;
-	struct pmgr_pmupstate *pmgr_pmu;
+	struct pmgr_pmupstate pmgr_pmu;
 	struct therm_pmupstate *therm_pmu;
 	struct nvgpu_sec2 sec2;
 
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index 5e25fac65..2c9c51373 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -46,7 +46,6 @@
 #include "dmabuf.h"
 #include "channel.h"
 #include "dmabuf_vidmem.h"
-#include "pmgr/pmgr.h"
 
 #define HZ_TO_MHZ(a) ((a > 0xF414F9CD7ULL) ? 0xffff : (a >> 32) ? \
 	(u32) ((a * 0x10C8ULL) >> 32) : (u16) ((u32) a/MHZ))
diff --git a/drivers/gpu/nvgpu/pmgr/pmgr.c b/drivers/gpu/nvgpu/pmgr/pmgr.c
index 9b3ee8844..8d7e4485c 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgr.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgr.c
@@ -22,7 +22,6 @@
 
 #include <nvgpu/gk20a.h>
 
-#include "pmgr.h"
 #include "pwrdev.h"
 #include "pmgrpmu.h"
 
@@ -110,23 +109,3 @@ int pmgr_domain_pmu_setup(struct gk20a *g)
 {
 	return pmgr_send_pmgr_tables_to_pmu(g);
 }
-
-int pmgr_pmu_init_pmupstate(struct gk20a *g)
-{
-	/* If already allocated, do not re-allocate */
-	if (g->pmgr_pmu != NULL) {
-		return 0;
-	}
-
-	g->pmgr_pmu = nvgpu_kzalloc(g, sizeof(*g->pmgr_pmu));
-	if (g->pmgr_pmu == NULL) {
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-void pmgr_pmu_free_pmupstate(struct gk20a *g)
-{
-	nvgpu_kfree(g, g->pmgr_pmu);
-}
diff --git a/drivers/gpu/nvgpu/pmgr/pmgr.h b/drivers/gpu/nvgpu/pmgr/pmgr.h
index b22a48b85..fddfb574a 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgr.h
+++ b/drivers/gpu/nvgpu/pmgr/pmgr.h
@@ -39,7 +39,5 @@ int pmgr_domain_pmu_setup(struct gk20a *g);
 int pmgr_pwr_devices_get_current(struct gk20a *g, u32 *val);
 int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val);
 int pmgr_pwr_devices_get_power(struct gk20a *g, u32 *val);
-int pmgr_pmu_init_pmupstate(struct gk20a *g);
-void pmgr_pmu_free_pmupstate(struct gk20a *g);
 
 #endif /* NVGPU_PMGR_H */
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
index 115bd16dd..7baec4972 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
@@ -31,7 +31,6 @@
 #include "gp106/bios_gp106.h"
 
 #include "pwrdev.h"
-#include "pmgr.h"
 #include "pmgrpmu.h"
 
 struct pmgr_pmucmdhandler_params {
@@ -195,10 +194,10 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g)
 
 	/* populate the table */
 	boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)&ppwr_desc_header->super,
-			g->pmgr_pmu->pmgr_deviceobjs.super.super.objmask);
+			g->pmgr_pmu.pmgr_deviceobjs.super.super.objmask);
 
 	status = boardobjgrp_pmudatainit_legacy(g,
-			&g->pmgr_pmu->pmgr_deviceobjs.super.super,
+			&g->pmgr_pmu.pmgr_deviceobjs.super.super,
 			(struct nv_pmu_boardobjgrp_super *)pwr_desc_table);
 
 	if (status != 0) {
@@ -241,14 +240,14 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g)
 
 	/* Copy all the global settings from the RM copy */
 	pwr_channel_hdr = &(pwr_monitor_pack->channels.hdr.data);
-	*pwr_monitor_pack = g->pmgr_pmu->pmgr_monitorobjs.pmu_data;
+	*pwr_monitor_pack = g->pmgr_pmu.pmgr_monitorobjs.pmu_data;
 
 	boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)&pwr_channel_hdr->super,
-			g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super.objmask);
+			g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super.objmask);
 
 	/* Copy in each channel */
 	status = boardobjgrp_pmudatainit_legacy(g,
-			&g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super,
+			&g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super,
 			(struct nv_pmu_boardobjgrp_super *)&(pwr_monitor_pack->channels));
 
 	if (status != 0) {
@@ -261,14 +260,13 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g)
 	pwr_chrelationship_header =  &(pwr_monitor_pack->ch_rels.hdr.data);
 
 	boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)&pwr_chrelationship_header->super,
-			g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels.super.objmask);
+			g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels.super.objmask);
 
-	pwr_channel_hdr->physical_channel_mask =
-			g->pmgr_pmu->pmgr_monitorobjs.physical_channel_mask;
+	pwr_channel_hdr->physical_channel_mask = g->pmgr_pmu.pmgr_monitorobjs.physical_channel_mask;
 	pwr_channel_hdr->type = NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING;
 
 	status = boardobjgrp_pmudatainit_legacy(g,
-		&g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels.super,
+		&g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels.super,
 		(struct nv_pmu_boardobjgrp_super *)&(pwr_monitor_pack->ch_rels));
 
 	if (status != 0) {
@@ -314,31 +312,31 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g)
 		goto exit;
 	}
 
-	ppwrpack->policies.hdr.data.version = g->pmgr_pmu->pmgr_policyobjs.version;
-	ppwrpack->policies.hdr.data.b_enabled = g->pmgr_pmu->pmgr_policyobjs.b_enabled;
+	ppwrpack->policies.hdr.data.version = g->pmgr_pmu.pmgr_policyobjs.version;
+	ppwrpack->policies.hdr.data.b_enabled = g->pmgr_pmu.pmgr_policyobjs.b_enabled;
 
 	boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)
 			&ppwrpack->policies.hdr.data.super,
-			g->pmgr_pmu->pmgr_policyobjs.pwr_policies.super.objmask);
+			g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super.objmask);
 
 	(void) memset(&ppwrpack->policies.hdr.data.reserved_pmu_policy_mask,
 			0,
 			sizeof(ppwrpack->policies.hdr.data.reserved_pmu_policy_mask));
 
 	ppwrpack->policies.hdr.data.base_sample_period =
-			g->pmgr_pmu->pmgr_policyobjs.base_sample_period;
+			g->pmgr_pmu.pmgr_policyobjs.base_sample_period;
 	ppwrpack->policies.hdr.data.min_client_sample_period =
-			g->pmgr_pmu->pmgr_policyobjs.min_client_sample_period;
+			g->pmgr_pmu.pmgr_policyobjs.min_client_sample_period;
 	ppwrpack->policies.hdr.data.low_sampling_mult =
-			g->pmgr_pmu->pmgr_policyobjs.low_sampling_mult;
+			g->pmgr_pmu.pmgr_policyobjs.low_sampling_mult;
 
 	nvgpu_memcpy((u8 *)&ppwrpack->policies.hdr.data.global_ceiling,
-			(u8 *)&g->pmgr_pmu->pmgr_policyobjs.global_ceiling,
+			(u8 *)&g->pmgr_pmu.pmgr_policyobjs.global_ceiling,
 			sizeof(struct nv_pmu_perf_domain_group_limits));
 
 	nvgpu_memcpy((u8 *)&ppwrpack->policies.hdr.data.semantic_policy_tbl,
-			(u8 *)&g->pmgr_pmu->pmgr_policyobjs.policy_idxs,
-			sizeof(g->pmgr_pmu->pmgr_policyobjs.policy_idxs));
+			(u8 *)&g->pmgr_pmu.pmgr_policyobjs.policy_idxs,
+			sizeof(g->pmgr_pmu.pmgr_policyobjs.policy_idxs));
 
 	BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(32, indx,
 			ppwrpack->policies.hdr.data.super.obj_mask.super.data[0]) {
@@ -357,11 +355,11 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g)
 
 	boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)
 			&ppwrpack->policy_rels.hdr.data.super,
-			g->pmgr_pmu->pmgr_policyobjs.pwr_policy_rels.super.objmask);
+			g->pmgr_pmu.pmgr_policyobjs.pwr_policy_rels.super.objmask);
 
 	boardobjgrpe32hdrset((struct nv_pmu_boardobjgrp *)
 			&ppwrpack->violations.hdr.data.super,
-			g->pmgr_pmu->pmgr_policyobjs.pwr_violations.super.objmask);
+			g->pmgr_pmu.pmgr_policyobjs.pwr_violations.super.objmask);
 
 	max_dmem_size = sizeof(union nv_pmu_pmgr_pwr_policy_dmem_size);
 
@@ -502,7 +500,7 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g)
 		goto exit;
 	}
 
-	if (!BOARDOBJGRP_IS_EMPTY(&g->pmgr_pmu->pmgr_deviceobjs.super.super)) {
+	if (!BOARDOBJGRP_IS_EMPTY(&g->pmgr_pmu.pmgr_deviceobjs.super.super)) {
 		status = pmgr_send_pwr_device_topology_to_pmu(g);
 		if (status != 0) {
 			nvgpu_err(g,
@@ -513,9 +511,9 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g)
 	}
 
 	if (!(BOARDOBJGRP_IS_EMPTY(
-			&g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super)) ||
+			&g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super)) ||
 		!(BOARDOBJGRP_IS_EMPTY(
-			&g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels.super))) {
+			&g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels.super))) {
 		status = pmgr_send_pwr_mointer_to_pmu(g);
 		if (status != 0) {
 			nvgpu_err(g,
@@ -525,11 +523,11 @@ int pmgr_send_pmgr_tables_to_pmu(struct gk20a *g)
 	}
 
 	if (!(BOARDOBJGRP_IS_EMPTY(
-			&g->pmgr_pmu->pmgr_policyobjs.pwr_policies.super)) ||
+			&g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super)) ||
 		!(BOARDOBJGRP_IS_EMPTY(
-			&g->pmgr_pmu->pmgr_policyobjs.pwr_policy_rels.super)) ||
+			&g->pmgr_pmu.pmgr_policyobjs.pwr_policy_rels.super)) ||
 		!(BOARDOBJGRP_IS_EMPTY(
-			&g->pmgr_pmu->pmgr_policyobjs.pwr_violations.super))) {
+			&g->pmgr_pmu.pmgr_policyobjs.pwr_violations.super))) {
 		status = pmgr_send_pwr_policy_to_pmu(g);
 		if (status != 0) {
 			nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c
index 06a1d40e0..547edd153 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrdev.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c
@@ -27,7 +27,6 @@
 #include <nvgpu/string.h>
 
 #include "pwrdev.h"
-#include "pmgr.h"
 #include "gp106/bios_gp106.h"
 
 static int _pwr_device_pmudata_instget(struct gk20a *g,
@@ -296,7 +295,7 @@ int pmgr_device_sw_setup(struct gk20a *g)
 	struct pwr_devices *ppwrdeviceobjs;
 
 	/* Construct the Super Class and override the Interfaces */
-	status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu->pmgr_deviceobjs.super);
+	status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu.pmgr_deviceobjs.super);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for pmgr devices, status - 0x%x",
@@ -304,8 +303,8 @@ int pmgr_device_sw_setup(struct gk20a *g)
 		goto done;
 	}
 
-	pboardobjgrp = &g->pmgr_pmu->pmgr_deviceobjs.super.super;
-	ppwrdeviceobjs = &(g->pmgr_pmu->pmgr_deviceobjs);
+	pboardobjgrp = &g->pmgr_pmu.pmgr_deviceobjs.super.super;
+	ppwrdeviceobjs = &(g->pmgr_pmu.pmgr_deviceobjs);
 
 	/* Override the Interfaces */
 	pboardobjgrp->pmudatainstget = _pwr_device_pmudata_instget;
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
index 07a4ce72b..304038952 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
@@ -27,7 +27,6 @@
 #include <nvgpu/string.h>
 
 #include "pwrdev.h"
-#include "pmgr.h"
 #include "gp106/bios_gp106.h"
 
 static int _pwr_channel_pmudata_instget(struct gk20a *g,
@@ -86,7 +85,7 @@ static u32 _pwr_channel_state_init(struct gk20a *g)
 	u8 indx = 0;
 	struct pwr_channel *pchannel;
 	u32 objmask =
-		g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super.objmask;
+		g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super.objmask;
 
 	/* Initialize each PWR_CHANNEL's dependent channel mask */
 	BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(32, indx, objmask) {
@@ -215,7 +214,7 @@ static int devinit_get_pwr_topology_table(struct gk20a *g,
 		goto done;
 	}
 
-	g->pmgr_pmu->pmgr_monitorobjs.b_is_topology_tbl_ver_1x = false;
+	g->pmgr_pmu.pmgr_monitorobjs.b_is_topology_tbl_ver_1x = false;
 
 	if (pwr_topology_table_header.header_size <
 			VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06) {
@@ -312,7 +311,7 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
 
 	/* Construct the Super Class and override the Interfaces */
 	status = boardobjgrpconstruct_e32(g,
-			&g->pmgr_pmu->pmgr_monitorobjs.pwr_channels);
+			&g->pmgr_pmu.pmgr_monitorobjs.pwr_channels);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for pmgr channel, status - 0x%x",
@@ -320,14 +319,14 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
 		goto done;
 	}
 
-	pboardobjgrp = &(g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super);
+	pboardobjgrp = &(g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super);
 
 	/* Override the Interfaces */
 	pboardobjgrp->pmudatainstget = _pwr_channel_pmudata_instget;
 
 	/* Construct the Super Class and override the Interfaces */
 	status = boardobjgrpconstruct_e32(g,
-			&g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels);
+			&g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for pmgr channel relationship, status - 0x%x",
@@ -335,20 +334,20 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
 		goto done;
 	}
 
-	pboardobjgrp = &(g->pmgr_pmu->pmgr_monitorobjs.pwr_ch_rels.super);
+	pboardobjgrp = &(g->pmgr_pmu.pmgr_monitorobjs.pwr_ch_rels.super);
 
 	/* Override the Interfaces */
 	pboardobjgrp->pmudatainstget = _pwr_channel_rels_pmudata_instget;
 
 	/* Initialize the Total GPU Power Channel Mask to 0 */
-	g->pmgr_pmu->pmgr_monitorobjs.pmu_data.channels.hdr.data.total_gpu_power_channel_mask = 0;
-	g->pmgr_pmu->pmgr_monitorobjs.total_gpu_channel_idx =
+	g->pmgr_pmu.pmgr_monitorobjs.pmu_data.channels.hdr.data.total_gpu_power_channel_mask = 0;
+	g->pmgr_pmu.pmgr_monitorobjs.total_gpu_channel_idx =
 			CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID;
 
 	/* Supported topology table version 1.0 */
-	g->pmgr_pmu->pmgr_monitorobjs.b_is_topology_tbl_ver_1x = true;
+	g->pmgr_pmu.pmgr_monitorobjs.b_is_topology_tbl_ver_1x = true;
 
-	ppwrmonitorobjs = &(g->pmgr_pmu->pmgr_monitorobjs);
+	ppwrmonitorobjs = &(g->pmgr_pmu.pmgr_monitorobjs);
 
 	status = devinit_get_pwr_topology_table(g, ppwrmonitorobjs);
 	if (status != 0) {
@@ -361,14 +360,14 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
 	}
 
 	/* Initialise physicalChannelMask */
-	g->pmgr_pmu->pmgr_monitorobjs.physical_channel_mask = 0;
+	g->pmgr_pmu.pmgr_monitorobjs.physical_channel_mask = 0;
 
-	pboardobjgrp = &g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super;
+	pboardobjgrp = &g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super;
 
 	BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct pwr_channel *, pchannel, indx) {
 		if (_pwr_channel_implements(pchannel,
 				CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR)) {
-			g->pmgr_pmu->pmgr_monitorobjs.physical_channel_mask  |= BIT(indx);
+			g->pmgr_pmu.pmgr_monitorobjs.physical_channel_mask  |= BIT(indx);
 		}
 	}
 
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
index 4a4832fac..866aef9f9 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
+++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
@@ -62,7 +62,7 @@ struct pmgr_pwr_monitor {
 
 #define PMGR_PWR_MONITOR_GET_PWR_CHANNEL(g, channel_idx)                    \
 	((struct pwr_channel *)BOARDOBJGRP_OBJ_GET_BY_IDX(                                 \
-		&(g->pmgr_pmu->pmgr_monitorobjs.pwr_channels.super), (channel_idx)))
+		&(g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super), (channel_idx)))
 
 int pmgr_monitor_sw_setup(struct gk20a *g);
 
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
index 682923883..bbc486dff 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
@@ -28,7 +28,6 @@
 #include <nvgpu/string.h>
 
 #include "pwrpolicy.h"
-#include "pmgr.h"
 #include "gp106/bios_gp106.h"
 
 #define _pwr_policy_limitarboutputget_helper(p_limit_arb) (p_limit_arb)->output
@@ -724,7 +723,7 @@ int pmgr_policy_sw_setup(struct gk20a *g)
 
 	/* Construct the Super Class and override the Interfaces */
 	status = boardobjgrpconstruct_e32(g,
-			&g->pmgr_pmu->pmgr_policyobjs.pwr_policies);
+			&g->pmgr_pmu.pmgr_policyobjs.pwr_policies);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for pmgr policy, status - 0x%x",
@@ -733,7 +732,7 @@ int pmgr_policy_sw_setup(struct gk20a *g)
 	}
 
 	status = boardobjgrpconstruct_e32(g,
-			&g->pmgr_pmu->pmgr_policyobjs.pwr_policy_rels);
+			&g->pmgr_pmu.pmgr_policyobjs.pwr_policy_rels);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for pmgr policy rels, status - 0x%x",
@@ -742,7 +741,7 @@ int pmgr_policy_sw_setup(struct gk20a *g)
 	}
 
 	status = boardobjgrpconstruct_e32(g,
-			&g->pmgr_pmu->pmgr_policyobjs.pwr_violations);
+			&g->pmgr_pmu.pmgr_policyobjs.pwr_violations);
 	if (status != 0) {
 		nvgpu_err(g,
 			"error creating boardobjgrp for pmgr violations, status - 0x%x",
@@ -750,37 +749,37 @@ int pmgr_policy_sw_setup(struct gk20a *g)
 		goto done;
 	}
 
-	(void) memset(g->pmgr_pmu->pmgr_policyobjs.policy_idxs,
+	(void) memset(g->pmgr_pmu.pmgr_policyobjs.policy_idxs,
 		CTRL_PMGR_PWR_POLICY_INDEX_INVALID,
 		sizeof(u8) * CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES);
 
 	/* Initialize external power limit policy indexes to _INVALID/0xFF */
 	for (indx = 0; indx < PWR_POLICY_EXT_POWER_STATE_ID_COUNT; indx++) {
-		g->pmgr_pmu->pmgr_policyobjs.ext_limits[indx].policy_table_idx =
+		g->pmgr_pmu.pmgr_policyobjs.ext_limits[indx].policy_table_idx =
 			CTRL_PMGR_PWR_POLICY_INDEX_INVALID;
 	}
 
 	/* Initialize external power state to _D1 */
-	g->pmgr_pmu->pmgr_policyobjs.ext_power_state = 0xFFFFFFFF;
+	g->pmgr_pmu.pmgr_policyobjs.ext_power_state = 0xFFFFFFFF;
 
-	ppwrpolicyobjs = &(g->pmgr_pmu->pmgr_policyobjs);
-	pboardobjgrp = &(g->pmgr_pmu->pmgr_policyobjs.pwr_policies.super);
+	ppwrpolicyobjs = &(g->pmgr_pmu.pmgr_policyobjs);
+	pboardobjgrp = &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super);
 
 	status = devinit_get_pwr_policy_table(g, ppwrpolicyobjs);
 	if (status != 0) {
 		goto done;
 	}
 
-	g->pmgr_pmu->pmgr_policyobjs.b_enabled = true;
+	g->pmgr_pmu.pmgr_policyobjs.b_enabled = true;
 
 	BOARDOBJGRP_FOR_EACH(pboardobjgrp, struct pwr_policy *, ppolicy, indx) {
 		PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy);
 	}
 
-	g->pmgr_pmu->pmgr_policyobjs.global_ceiling.values[0] =
+	g->pmgr_pmu.pmgr_policyobjs.global_ceiling.values[0] =
 				0xFF;
 
-	g->pmgr_pmu->pmgr_policyobjs.client_work_item.b_pending = false;
+	g->pmgr_pmu.pmgr_policyobjs.client_work_item.b_pending = false;
 
 done:
 	nvgpu_log_info(g, " done status %x", status);
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
index 32cacf0eb..31748978e 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
@@ -126,7 +126,7 @@ union pwr_policy_data_union {
 
 #define PMGR_GET_PWR_POLICY(g, policy_idx)                                 \
 	((struct pwr_policy *)BOARDOBJGRP_OBJ_GET_BY_IDX(                                 \
-		&(g->pmgr_pmu->pmgr_policyobjs.pwr_policies.super), (policy_idx)))
+		&(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super), (policy_idx)))
 
 #define PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy)                 \
 	((ppolicy)->num_limit_inputs++)
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index 208df6477..a2cce532a 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -36,7 +36,6 @@ static int pstate_sw_setup(struct gk20a *g);
 
 void gk20a_deinit_pstate_support(struct gk20a *g)
 {
-	pmgr_pmu_free_pmupstate(g);
 	therm_pmu_free_pmupstate(g);
 	perf_pmu_free_pmupstate(g);
 	clk_free_pmupstate(g);
@@ -70,96 +69,89 @@ int gk20a_init_pstate_support(struct gk20a *g)
 		goto err_perf_pmu_init_pmupstate;
 	}
 
-	err = pmgr_pmu_init_pmupstate(g);
+	err = volt_rail_sw_setup(g);
 	if (err != 0) {
 		goto err_therm_pmu_init_pmupstate;
 	}
 
-	err = volt_rail_sw_setup(g);
-	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
-	}
-
 	err = volt_dev_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = volt_policy_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = clk_vin_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = clk_fll_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = therm_domain_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = vfe_var_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = vfe_equ_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = clk_domain_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = clk_vf_point_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = clk_prog_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	err = pstate_sw_setup(g);
 	if (err != 0) {
-		goto err_pmgr_pmu_init_pmupstate;
+		goto err_therm_pmu_init_pmupstate;
 	}
 
 	if(g->ops.clk.support_pmgr_domain) {
 		err = pmgr_domain_sw_setup(g);
 		if (err != 0) {
-			goto err_pmgr_pmu_init_pmupstate;
+			goto err_therm_pmu_init_pmupstate;
 		}
 	}
 
 	if (g->ops.clk.support_clk_freq_controller) {
 		err = clk_freq_controller_sw_setup(g);
 		if (err != 0) {
-			goto err_pmgr_pmu_init_pmupstate;
+			goto err_therm_pmu_init_pmupstate;
 		}
 	}
 
 	if(g->ops.clk.support_lpwr_pg) {
 		err = nvgpu_lpwr_pg_setup(g);
 		if (err != 0) {
-			goto err_pmgr_pmu_init_pmupstate;
+			goto err_therm_pmu_init_pmupstate;
 		}
 	}
 
 	return 0;
 
-err_pmgr_pmu_init_pmupstate:
-	pmgr_pmu_free_pmupstate(g);
 err_therm_pmu_init_pmupstate:
 	therm_pmu_free_pmupstate(g);
 err_perf_pmu_init_pmupstate: