diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 8e310d362..6e0eef3f5 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -343,6 +343,7 @@ nvgpu-y += \
 	common/fifo/channel_gv11b.o \
 	common/fifo/channel_gv100.o \
 	common/fifo/engine_status.o \
+	common/fifo/engines.o \
 	common/fifo/engine_status_gm20b.o \
 	common/fifo/engine_status_gv100.o \
 	common/ecc.o \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index cd883378f..c6adeaf22 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -187,6 +187,7 @@ srcs += common/sim.c \
 	common/fifo/channel_gv11b.c \
 	common/fifo/channel_gv100.c \
 	common/fifo/engine_status.c \
+	common/fifo/engines.c \
 	common/fifo/engine_status_gm20b.c \
 	common/fifo/engine_status_gv100.c \
 	common/mc/mc.c \
diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
new file mode 100644
index 000000000..3602b0f3a
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/engines.h>
+#include <nvgpu/gk20a.h>
+
+enum nvgpu_fifo_engine nvgpu_engine_enum_from_type(struct gk20a *g,
+					u32 engine_type)
+{
+	enum nvgpu_fifo_engine ret = NVGPU_ENGINE_INVAL_GK20A;
+
+	if ((g->ops.top.is_engine_gr != NULL) &&
+					(g->ops.top.is_engine_ce != NULL)) {
+		if (g->ops.top.is_engine_gr(g, engine_type)) {
+			ret = NVGPU_ENGINE_GR_GK20A;
+		} else if (g->ops.top.is_engine_ce(g, engine_type)) {
+			/* Lets consider all the CE engine have separate
+			 * runlist at this point. We can identify the
+			 * NVGPU_ENGINE_GRCE_GK20A type CE using runlist_id
+			 * comparsion logic with GR runlist_id in
+			 * init_engine_info()
+			 */
+			ret = NVGPU_ENGINE_ASYNC_CE_GK20A;
+		} else {
+			ret = NVGPU_ENGINE_INVAL_GK20A;
+		}
+	}
+
+	return ret;
+}
+
+struct fifo_engine_info_gk20a *nvgpu_engine_get_active_eng_info(
+	struct gk20a *g, u32 engine_id)
+{
+	struct fifo_gk20a *f = NULL;
+	u32 engine_id_idx;
+	struct fifo_engine_info_gk20a *info = NULL;
+
+	if (g == NULL) {
+		return info;
+	}
+
+	f = &g->fifo;
+
+	if (engine_id < f->max_engines) {
+		for (engine_id_idx = 0; engine_id_idx < f->num_engines;
+				++engine_id_idx) {
+			if (engine_id ==
+					f->active_engines_list[engine_id_idx]) {
+				info = &f->engine_info[engine_id];
+				break;
+			}
+		}
+	}
+
+	if (info == NULL) {
+		nvgpu_err(g, "engine_id is not in active list/invalid %d",
+			engine_id);
+	}
+
+	return info;
+}
+
+u32 nvgpu_engine_get_ids(struct gk20a *g,
+		u32 engine_id[], u32 engine_id_sz,
+		enum nvgpu_fifo_engine engine_enum)
+{
+	struct fifo_gk20a *f = NULL;
+	u32 instance_cnt = 0;
+	u32 engine_id_idx;
+	u32 active_engine_id = 0;
+	struct fifo_engine_info_gk20a *info = NULL;
+
+	if ((g == NULL) || (engine_id_sz == 0U) ||
+			(engine_enum == NVGPU_ENGINE_INVAL_GK20A)) {
+		return instance_cnt;
+	}
+
+	f = &g->fifo;
+	for (engine_id_idx = 0; engine_id_idx < f->num_engines;
+			 ++engine_id_idx) {
+		active_engine_id = f->active_engines_list[engine_id_idx];
+		info = &f->engine_info[active_engine_id];
+
+		if (info->engine_enum == engine_enum) {
+			if (instance_cnt < engine_id_sz) {
+				engine_id[instance_cnt] = active_engine_id;
+				++instance_cnt;
+			} else {
+				nvgpu_log_info(g, "warning engine_id table sz is small %d",
+					engine_id_sz);
+			}
+		}
+	}
+	return instance_cnt;
+}
+
+bool nvgpu_engine_check_valid_eng_id(struct gk20a *g, u32 engine_id)
+{
+	struct fifo_gk20a *f = NULL;
+	u32 engine_id_idx;
+	bool valid = false;
+
+	if (g == NULL) {
+		return valid;
+	}
+
+	f = &g->fifo;
+
+	if (engine_id < f->max_engines) {
+		for (engine_id_idx = 0; engine_id_idx < f->num_engines;
+				++engine_id_idx) {
+			if (engine_id == f->active_engines_list[engine_id_idx]) {
+				valid = true;
+				break;
+			}
+		}
+	}
+
+	if (!valid) {
+		nvgpu_err(g, "engine_id is not in active list/invalid %d",
+			engine_id);
+	}
+
+	return valid;
+}
+
+u32 nvgpu_engine_get_gr_eng_id(struct gk20a *g)
+{
+	u32 gr_engine_cnt = 0;
+	u32 gr_engine_id = FIFO_INVAL_ENGINE_ID;
+
+	/* Consider 1st available GR engine */
+	gr_engine_cnt = nvgpu_engine_get_ids(g, &gr_engine_id,
+			1, NVGPU_ENGINE_GR_GK20A);
+
+	if (gr_engine_cnt == 0U) {
+		nvgpu_err(g, "No GR engine available on this device!");
+	}
+
+	return gr_engine_id;
+}
+
+u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 act_eng_id)
+{
+	struct fifo_engine_info_gk20a *engine_info = NULL;
+
+	engine_info = nvgpu_engine_get_active_eng_info(g, act_eng_id);
+	if (engine_info != NULL) {
+		return engine_info->intr_mask;
+	}
+
+	return 0;
+}
+
+u32 nvgpu_engine_interrupt_mask(struct gk20a *g)
+{
+	u32 eng_intr_mask = 0;
+	unsigned int i;
+	u32 active_engine_id = 0;
+	enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A;
+
+	for (i = 0; i < g->fifo.num_engines; i++) {
+		u32 intr_mask;
+		active_engine_id = g->fifo.active_engines_list[i];
+		intr_mask = g->fifo.engine_info[active_engine_id].intr_mask;
+		engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
+		if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
+		     (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
+		    ((g->ops.ce2.isr_stall == NULL) ||
+		     (g->ops.ce2.isr_nonstall == NULL))) {
+				continue;
+		}
+
+		eng_intr_mask |= intr_mask;
+	}
+
+	return eng_intr_mask;
+}
+
+u32 nvgpu_engine_get_all_ce_eng_reset_mask(struct gk20a *g)
+{
+	u32 reset_mask = 0;
+	enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A;
+	struct fifo_gk20a *f = NULL;
+	u32 engine_id_idx;
+	struct fifo_engine_info_gk20a *engine_info;
+	u32 active_engine_id = 0;
+
+	if (g == NULL) {
+		return reset_mask;
+	}
+
+	f = &g->fifo;
+
+	for (engine_id_idx = 0; engine_id_idx < f->num_engines;
+			++engine_id_idx) {
+		active_engine_id = f->active_engines_list[engine_id_idx];
+		engine_info = &f->engine_info[active_engine_id];
+		engine_enum = engine_info->engine_enum;
+
+		if ((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
+			(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) {
+				reset_mask |= engine_info->reset_mask;
+		}
+	}
+
+	return reset_mask;
+}
\ No newline at end of file
diff --git a/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c b/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
index 3a1b71f48..0e698adc5 100644
--- a/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
+++ b/drivers/gpu/nvgpu/common/fifo/runlist_gk20a.c
@@ -25,6 +25,7 @@
 #include <nvgpu/runlist.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/engine_status.h>
+#include <nvgpu/engines.h>
 
 #include <gk20a/fifo_gk20a.h>
 
@@ -56,8 +57,8 @@ int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
 	u32 preempt_type = 0;
 	struct nvgpu_engine_status_info engine_status;
 
-	if (1U != gk20a_fifo_get_engine_ids(
-		g, &gr_eng_id, 1, ENGINE_GR_GK20A)) {
+	if (1U != nvgpu_engine_get_ids(
+		g, &gr_eng_id, 1, NVGPU_ENGINE_GR_GK20A)) {
 		return ret;
 	}
 	if ((runlist->eng_bitmask & BIT32(gr_eng_id)) == 0U) {
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c
index 5f56858bb..66cfe647c 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c
+++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c
@@ -29,6 +29,7 @@
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/engines.h>
 
 #include "mc_gm20b.h"
 
@@ -39,7 +40,7 @@ void gm20b_mc_isr_stall(struct gk20a *g)
 	u32 mc_intr_0;
 	u32 engine_id_idx;
 	u32 active_engine_id = 0;
-	u32 engine_enum = ENGINE_INVAL_GK20A;
+	u32 engine_enum = NVGPU_ENGINE_INVAL_GK20A;
 
 	mc_intr_0 = g->ops.mc.intr_stall(g);
 
@@ -51,13 +52,13 @@ void gm20b_mc_isr_stall(struct gk20a *g)
 		if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
 			engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
 			/* GR Engine */
-			if (engine_enum == ENGINE_GR_GK20A) {
+			if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
 				gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
 			}
 
 			/* CE Engine */
-			if (((engine_enum == ENGINE_GRCE_GK20A) ||
-				(engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
+			if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
+				(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
 				(g->ops.ce2.isr_stall != NULL)) {
 					g->ops.ce2.isr_stall(g,
 					g->fifo.engine_info[active_engine_id].inst_id,
@@ -88,7 +89,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g)
 	u32 mc_intr_1;
 	u32 engine_id_idx;
 	u32 active_engine_id = 0;
-	u32 engine_enum = ENGINE_INVAL_GK20A;
+	u32 engine_enum = NVGPU_ENGINE_INVAL_GK20A;
 
 	mc_intr_1 = g->ops.mc.intr_nonstall(g);
 
@@ -106,12 +107,12 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g)
 		if ((mc_intr_1 & engine_info->intr_mask) != 0U) {
 			engine_enum = engine_info->engine_enum;
 			/* GR Engine */
-			if (engine_enum == ENGINE_GR_GK20A) {
+			if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
 				ops |= gk20a_gr_nonstall_isr(g);
 			}
 			/* CE Engine */
-			if (((engine_enum == ENGINE_GRCE_GK20A) ||
-			     (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
+			if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
+			     (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
 			      (g->ops.ce2.isr_nonstall != NULL)) {
 				ops |= g->ops.ce2.isr_nonstall(g,
 					engine_info->inst_id,
@@ -133,7 +134,7 @@ void gm20b_mc_intr_mask(struct gk20a *g)
 
 void gm20b_mc_intr_enable(struct gk20a *g)
 {
-	u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
 	gk20a_writel(g, mc_intr_mask_1_r(),
 		     mc_intr_pfifo_pending_f()
@@ -246,7 +247,7 @@ void gm20b_mc_enable(struct gk20a *g, u32 units)
 void gm20b_mc_reset(struct gk20a *g, u32 units)
 {
 	g->ops.mc.disable(g, units);
-	if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) {
+	if ((units & nvgpu_engine_get_all_ce_eng_reset_mask(g)) != 0U) {
 		nvgpu_udelay(500);
 	} else {
 		nvgpu_udelay(20);
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c
index 397681aae..c4c8568b8 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c
@@ -25,6 +25,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/io.h>
 #include <nvgpu/mc.h>
+#include <nvgpu/engines.h>
 
 #include "mc_gp10b.h"
 
@@ -46,7 +47,7 @@ void mc_gp10b_intr_mask(struct gk20a *g)
 
 void mc_gp10b_intr_enable(struct gk20a *g)
 {
-	u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
 	gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
 				0xffffffffU);
@@ -95,7 +96,7 @@ void mc_gp10b_isr_stall(struct gk20a *g)
 
 	u32 engine_id_idx;
 	u32 active_engine_id = 0;
-	u32 engine_enum = ENGINE_INVAL_GK20A;
+	u32 engine_enum = NVGPU_ENGINE_INVAL_GK20A;
 
 	mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
 
@@ -107,13 +108,13 @@ void mc_gp10b_isr_stall(struct gk20a *g)
 		if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
 			engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
 			/* GR Engine */
-			if (engine_enum == ENGINE_GR_GK20A) {
+			if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
 				gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
 			}
 
 			/* CE Engine */
-			if (((engine_enum == ENGINE_GRCE_GK20A) ||
-				(engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
+			if (((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
+				(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) &&
 				(g->ops.ce2.isr_stall != NULL)) {
 					g->ops.ce2.isr_stall(g,
 					g->fifo.engine_info[active_engine_id].inst_id,
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c
index 77155d146..89bb5d0d0 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gv100.c
+++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c
@@ -28,6 +28,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/unit.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/engines.h>
 
 #include "mc_gp10b.h"
 #include "mc_gv100.h"
@@ -36,7 +37,7 @@
 
 void mc_gv100_intr_enable(struct gk20a *g)
 {
-	u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
 	gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
 				0xffffffffU);
@@ -74,7 +75,7 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
 	u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
 	u32 stall_intr, eng_intr_mask;
 
-	eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
+	eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id);
 	*eng_intr_pending = mc_intr_0 & eng_intr_mask;
 
 	stall_intr = mc_intr_pfifo_pending_f() |
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv11b.c b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c
index 35508bbec..9ea171dc6 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c
@@ -26,6 +26,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/engines.h>
 
 #include "mc_gp10b.h"
 #include "mc_gv11b.h"
@@ -34,7 +35,7 @@
 
 void mc_gv11b_intr_enable(struct gk20a *g)
 {
-	u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
 	gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
 				0xffffffffU);
@@ -72,7 +73,7 @@ bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
 	u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
 	u32 stall_intr, eng_intr_mask;
 
-	eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
+	eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id);
 	*eng_intr_pending = mc_intr_0 & eng_intr_mask;
 
 	stall_intr = mc_intr_pfifo_pending_f() |
diff --git a/drivers/gpu/nvgpu/common/mc/mc_tu104.c b/drivers/gpu/nvgpu/common/mc/mc_tu104.c
index 20edba428..a8e3e0e7b 100644
--- a/drivers/gpu/nvgpu/common/mc/mc_tu104.c
+++ b/drivers/gpu/nvgpu/common/mc/mc_tu104.c
@@ -25,6 +25,7 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/engines.h>
 
 #include "common/mc/mc_gp10b.h"
 #include "mc_tu104.h"
@@ -134,7 +135,7 @@ bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector)
 
 static void intr_tu104_stall_enable(struct gk20a *g)
 {
-	u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
 	nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
 				0xffffffffU);
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
index 270c446e1..9f32b2753 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
@@ -28,6 +28,7 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/string.h>
+#include <nvgpu/engines.h>
 
 /* state transition :
  * OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
@@ -554,7 +555,7 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g)
 
 	nvgpu_log_fn(g, " ");
 
-	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
+	gr_engine_id = nvgpu_engine_get_gr_eng_id(g);
 
 	(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
 	cmd.hdr.unit_id = PMU_UNIT_PG;
@@ -595,7 +596,7 @@ void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g)
 	u32 gr_engine_id;
 	int err = 0;
 
-	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
+	gr_engine_id = nvgpu_engine_get_gr_eng_id(g);
 
 	(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
 	cmd.hdr.unit_id = PMU_UNIT_PG;
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index 31ce2d988..9a8d9bf6d 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -31,6 +31,7 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/engines.h>
 
 #include "gk20a/fence_gk20a.h"
 #include "gk20a/ce2_gk20a.h"
@@ -349,7 +350,7 @@ int gk20a_init_ce_support(struct gk20a *g)
 		g->ce_app = ce_app;
 	}
 
-	ce_reset_mask = gk20a_fifo_get_all_ce_engine_reset_mask(g);
+	ce_reset_mask = nvgpu_engine_get_all_ce_eng_reset_mask(g);
 
 	g->ops.mc.reset(g, ce_reset_mask);
 
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 3223666a7..8c0ad34a6 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -53,6 +53,7 @@
 #include <nvgpu/top.h>
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/engine_status.h>
+#include <nvgpu/engines.h>
 
 #include "mm_gk20a.h"
 
@@ -94,143 +95,10 @@ void nvgpu_report_host_error(struct gk20a *g, u32 inst,
 	}
 }
 
-u32 gk20a_fifo_get_engine_ids(struct gk20a *g,
-		u32 engine_id[], u32 engine_id_sz,
-		enum fifo_engine engine_enum)
-{
-	struct fifo_gk20a *f = NULL;
-	u32 instance_cnt = 0;
-	u32 engine_id_idx;
-	u32 active_engine_id = 0;
-	struct fifo_engine_info_gk20a *info = NULL;
-
-	if ((g != NULL) &&
-	    (engine_id_sz != 0U) &&
-	    (engine_enum < ENGINE_INVAL_GK20A)) {
-		f = &g->fifo;
-		for (engine_id_idx = 0; engine_id_idx < f->num_engines; ++engine_id_idx) {
-			active_engine_id = f->active_engines_list[engine_id_idx];
-			info = &f->engine_info[active_engine_id];
-
-			if (info->engine_enum == engine_enum) {
-				if (instance_cnt < engine_id_sz) {
-					engine_id[instance_cnt] = active_engine_id;
-					++instance_cnt;
-				} else {
-					nvgpu_log_info(g, "warning engine_id table sz is small %d",
-							engine_id_sz);
-				}
-			}
-		}
-	}
-	return instance_cnt;
-}
-
-struct fifo_engine_info_gk20a *gk20a_fifo_get_engine_info(struct gk20a *g, u32 engine_id)
-{
-	struct fifo_gk20a *f = NULL;
-	u32 engine_id_idx;
-	struct fifo_engine_info_gk20a *info = NULL;
-
-	if (g == NULL) {
-		return info;
-	}
-
-	f = &g->fifo;
-
-	if (engine_id < f->max_engines) {
-		for (engine_id_idx = 0; engine_id_idx < f->num_engines; ++engine_id_idx) {
-			if (engine_id == f->active_engines_list[engine_id_idx]) {
-				info = &f->engine_info[engine_id];
-				break;
-			}
-		}
-	}
-
-	if (info == NULL) {
-		nvgpu_err(g, "engine_id is not in active list/invalid %d", engine_id);
-	}
-
-	return info;
-}
-
-bool gk20a_fifo_is_valid_engine_id(struct gk20a *g, u32 engine_id)
-{
-	struct fifo_gk20a *f = NULL;
-	u32 engine_id_idx;
-	bool valid = false;
-
-	if (g == NULL) {
-		return valid;
-	}
-
-	f = &g->fifo;
-
-	if (engine_id < f->max_engines) {
-		for (engine_id_idx = 0; engine_id_idx < f->num_engines; ++engine_id_idx) {
-			if (engine_id == f->active_engines_list[engine_id_idx]) {
-				valid = true;
-				break;
-			}
-		}
-	}
-
-	if (!valid) {
-		nvgpu_err(g, "engine_id is not in active list/invalid %d", engine_id);
-	}
-
-	return valid;
-}
-
-u32 gk20a_fifo_get_gr_engine_id(struct gk20a *g)
-{
-	u32 gr_engine_cnt = 0;
-	u32 gr_engine_id = FIFO_INVAL_ENGINE_ID;
-
-	/* Consider 1st available GR engine */
-	gr_engine_cnt = gk20a_fifo_get_engine_ids(g, &gr_engine_id,
-			1, ENGINE_GR_GK20A);
-
-	if (gr_engine_cnt == 0U) {
-		nvgpu_err(g, "No GR engine available on this device!");
-	}
-
-	return gr_engine_id;
-}
-
-u32 gk20a_fifo_get_all_ce_engine_reset_mask(struct gk20a *g)
-{
-	u32 reset_mask = 0;
-	enum fifo_engine engine_enum = ENGINE_INVAL_GK20A;
-	struct fifo_gk20a *f = NULL;
-	u32 engine_id_idx;
-	struct fifo_engine_info_gk20a *engine_info;
-	u32 active_engine_id = 0;
-
-	if (g == NULL) {
-		return reset_mask;
-	}
-
-	f = &g->fifo;
-
-	for (engine_id_idx = 0; engine_id_idx < f->num_engines; ++engine_id_idx) {
-		active_engine_id = f->active_engines_list[engine_id_idx];
-		engine_info = &f->engine_info[active_engine_id];
-		engine_enum = engine_info->engine_enum;
-
-		if ((engine_enum == ENGINE_GRCE_GK20A) ||
-			(engine_enum == ENGINE_ASYNC_CE_GK20A)) {
-				reset_mask |= engine_info->reset_mask;
-		}
-	}
-
-	return reset_mask;
-}
-
 u32 gk20a_fifo_get_fast_ce_runlist_id(struct gk20a *g)
 {
 	u32 ce_runlist_id = gk20a_fifo_get_gr_runlist_id(g);
-	enum fifo_engine engine_enum = ENGINE_INVAL_GK20A;
+	enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A;
 	struct fifo_gk20a *f = NULL;
 	u32 engine_id_idx;
 	struct fifo_engine_info_gk20a *engine_info;
@@ -248,7 +116,7 @@ u32 gk20a_fifo_get_fast_ce_runlist_id(struct gk20a *g)
 		engine_enum = engine_info->engine_enum;
 
 		/* selecet last available ASYNC_CE if available */
-		if (engine_enum == ENGINE_ASYNC_CE_GK20A) {
+		if (engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) {
 			ce_runlist_id = engine_info->runlist_id;
 		}
 	}
@@ -264,8 +132,8 @@ u32 gk20a_fifo_get_gr_runlist_id(struct gk20a *g)
 	u32 gr_runlist_id = U32_MAX;
 
 	/* Consider 1st available GR engine */
-	gr_engine_cnt = gk20a_fifo_get_engine_ids(g, &gr_engine_id,
-			1, ENGINE_GR_GK20A);
+	gr_engine_cnt = nvgpu_engine_get_ids(g, &gr_engine_id,
+			1, NVGPU_ENGINE_GR_GK20A);
 
 	if (gr_engine_cnt == 0U) {
 		nvgpu_err(g,
@@ -273,7 +141,7 @@ u32 gk20a_fifo_get_gr_runlist_id(struct gk20a *g)
 		goto end;
 	}
 
-	engine_info = gk20a_fifo_get_engine_info(g, gr_engine_id);
+	engine_info = nvgpu_engine_get_active_eng_info(g, gr_engine_id);
 
 	if (engine_info != NULL) {
 		gr_runlist_id = engine_info->runlist_id;
@@ -301,7 +169,7 @@ bool gk20a_fifo_is_valid_runlist_id(struct gk20a *g, u32 runlist_id)
 
 	for (engine_id_idx = 0; engine_id_idx < f->num_engines; ++engine_id_idx) {
 		active_engine_id = f->active_engines_list[engine_id_idx];
-		engine_info = gk20a_fifo_get_engine_info(g, active_engine_id);
+		engine_info = nvgpu_engine_get_active_eng_info(g, active_engine_id);
 		if ((engine_info != NULL) &&
 		    (engine_info->runlist_id == runlist_id)) {
 			return true;
@@ -320,7 +188,7 @@ static inline u32 gk20a_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id)
 	u32 fault_id = FIFO_INVAL_ENGINE_ID;
 	struct fifo_engine_info_gk20a *engine_info;
 
-	engine_info = gk20a_fifo_get_engine_info(g, engine_id);
+	engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
 
 	if (engine_info != NULL) {
 		fault_id = engine_info->fault_id;
@@ -349,68 +217,6 @@ static inline u32 gk20a_mmu_id_to_engine_id(struct gk20a *g, u32 fault_id)
 	return active_engine_id;
 }
 
-enum fifo_engine gk20a_fifo_engine_enum_from_type(struct gk20a *g,
-					u32 engine_type)
-{
-	enum fifo_engine ret = ENGINE_INVAL_GK20A;
-
-	if ((g->ops.top.is_engine_gr != NULL) &&
-					(g->ops.top.is_engine_ce != NULL)) {
-		if (g->ops.top.is_engine_gr(g, engine_type)) {
-			ret = ENGINE_GR_GK20A;
-		} else if (g->ops.top.is_engine_ce(g, engine_type)) {
-			/* Lets consider all the CE engine have separate
-			 * runlist at this point. We can identify the
-			 * ENGINE_GRCE_GK20A type CE using runlist_id
-			 * comparsion logic with GR runlist_id in
-			 * init_engine_info()
-			 */
-			ret = ENGINE_ASYNC_CE_GK20A;
-		} else {
-			ret = ENGINE_INVAL_GK20A;
-		}
-	}
-
-	return ret;
-}
-
-u32 gk20a_fifo_act_eng_interrupt_mask(struct gk20a *g, u32 act_eng_id)
-{
-	struct fifo_engine_info_gk20a *engine_info = NULL;
-
-	engine_info = gk20a_fifo_get_engine_info(g, act_eng_id);
-	if (engine_info != NULL) {
-		return engine_info->intr_mask;
-	}
-
-	return 0;
-}
-
-u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g)
-{
-	u32 eng_intr_mask = 0;
-	unsigned int i;
-	u32 active_engine_id = 0;
-	enum fifo_engine engine_enum = ENGINE_INVAL_GK20A;
-
-	for (i = 0; i < g->fifo.num_engines; i++) {
-		u32 intr_mask;
-		active_engine_id = g->fifo.active_engines_list[i];
-		intr_mask = g->fifo.engine_info[active_engine_id].intr_mask;
-		engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
-		if (((engine_enum == ENGINE_GRCE_GK20A) ||
-		     (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
-		    ((g->ops.ce2.isr_stall == NULL) ||
-		     (g->ops.ce2.isr_nonstall == NULL))) {
-				continue;
-		}
-
-		eng_intr_mask |= intr_mask;
-	}
-
-	return eng_intr_mask;
-}
-
 static void gk20a_remove_fifo_support(struct fifo_gk20a *f)
 {
 	struct gk20a *g = f->g;
@@ -1104,7 +910,7 @@ void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
 
 void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
 {
-	enum fifo_engine engine_enum = ENGINE_INVAL_GK20A;
+	enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A;
 	struct fifo_engine_info_gk20a *engine_info;
 
 	nvgpu_log_fn(g, " ");
@@ -1113,17 +919,17 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
 		return;
 	}
 
-	engine_info = gk20a_fifo_get_engine_info(g, engine_id);
+	engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
 
 	if (engine_info != NULL) {
 		engine_enum = engine_info->engine_enum;
 	}
 
-	if (engine_enum == ENGINE_INVAL_GK20A) {
+	if (engine_enum == NVGPU_ENGINE_INVAL_GK20A) {
 		nvgpu_err(g, "unsupported engine_id %d", engine_id);
 	}
 
-	if (engine_enum == ENGINE_GR_GK20A) {
+	if (engine_enum == NVGPU_ENGINE_GR_GK20A) {
 		if (g->support_pmu && g->can_elpg) {
 			if (nvgpu_pmu_disable_elpg(g) != 0) {
 				nvgpu_err(g, "failed to set disable elpg");
@@ -1158,8 +964,8 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
 			nvgpu_pmu_enable_elpg(g);
 		}
 	}
-	if ((engine_enum == ENGINE_GRCE_GK20A) ||
-		(engine_enum == ENGINE_ASYNC_CE_GK20A)) {
+	if ((engine_enum == NVGPU_ENGINE_GRCE_GK20A) ||
+		(engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A)) {
 			g->ops.mc.reset(g, engine_info->reset_mask);
 	}
 }
@@ -1190,20 +996,20 @@ bool gk20a_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid)
 bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
 		u32 engine_subid, bool fake_fault)
 {
-	enum fifo_engine engine_enum = ENGINE_INVAL_GK20A;
+	enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A;
 	struct fifo_engine_info_gk20a *engine_info;
 
 	if (g == NULL) {
 		return false;
 	}
 
-	engine_info = gk20a_fifo_get_engine_info(g, engine_id);
+	engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
 
 	if (engine_info != NULL) {
 		engine_enum = engine_info->engine_enum;
 	}
 
-	if (engine_enum == ENGINE_INVAL_GK20A) {
+	if (engine_enum == NVGPU_ENGINE_INVAL_GK20A) {
 		return false;
 	}
 
@@ -1219,7 +1025,7 @@ bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
 		return false;
 	}
 
-	if (engine_enum != ENGINE_GR_GK20A) {
+	if (engine_enum != NVGPU_ENGINE_GR_GK20A) {
 		return false;
 	}
 
@@ -1919,7 +1725,7 @@ bool gk20a_fifo_handle_sched_error(struct gk20a *g)
 	engine_id = gk20a_fifo_get_failing_engine_data(g, &id, &is_tsg);
 
 	/* could not find the engine - should never happen */
-	if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) {
+	if (!nvgpu_engine_check_valid_eng_id(g, engine_id)) {
 		nvgpu_err(g, "fifo sched error : 0x%08x, failed to find engine",
 			sched_error);
 		ret = false;
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index 270d2f9fa..9e56218f4 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -26,6 +26,7 @@
 
 #include <nvgpu/kref.h>
 #include <nvgpu/fifo.h>
+#include <nvgpu/engines.h>
 
 struct gk20a_debug_output;
 struct mmu_fault_info;
@@ -90,13 +91,6 @@ struct fifo_runlist_info_gk20a {
 	struct nvgpu_mutex runlist_lock;
 };
 
-enum fifo_engine {
-	ENGINE_GR_GK20A	       = 0U,
-	ENGINE_GRCE_GK20A      = 1U,
-	ENGINE_ASYNC_CE_GK20A  = 2U,
-	ENGINE_INVAL_GK20A     = 3U,
-};
-
 struct fifo_pbdma_exception_info_gk20a {
 	u32 status_r; /* raw register value from hardware */
 	u32 id, next_id;
@@ -122,7 +116,7 @@ struct fifo_engine_info_gk20a {
 	u32 inst_id;
 	u32 pri_base;
 	u32 fault_id;
-	enum fifo_engine engine_enum;
+	enum nvgpu_fifo_engine engine_enum;
 	struct fifo_pbdma_exception_info_gk20a pbdma_exception_info;
 	struct fifo_engine_exception_info_gk20a engine_exception_info;
 };
@@ -286,8 +280,6 @@ void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g,
 		unsigned long fault_id);
 int gk20a_fifo_wait_engine_idle(struct gk20a *g);
 bool gk20a_fifo_is_engine_busy(struct gk20a *g);
-u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g);
-u32 gk20a_fifo_act_eng_interrupt_mask(struct gk20a *g, u32 act_eng_id);
 u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g);
 u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g,
 		u32 *__id, bool *__is_tsg);
@@ -295,23 +287,8 @@ void gk20a_fifo_abort_tsg(struct gk20a *g, struct tsg_gk20a *tsg, bool preempt);
 void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg);
 int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
 
-enum fifo_engine gk20a_fifo_engine_enum_from_type(struct gk20a *g,
-				u32 engine_type);
-
-u32 gk20a_fifo_get_engine_ids(struct gk20a *g, u32 engine_id[],
-			u32 engine_id_sz, enum fifo_engine engine_enum);
-
-struct fifo_engine_info_gk20a *gk20a_fifo_get_engine_info(struct gk20a *g,
-							 u32 engine_id);
-
-bool gk20a_fifo_is_valid_engine_id(struct gk20a *g, u32 engine_id);
-
-u32 gk20a_fifo_get_gr_engine_id(struct gk20a *g);
-
 int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch);
 
-u32 gk20a_fifo_get_all_ce_engine_reset_mask(struct gk20a *g);
-
 u32 gk20a_fifo_get_fast_ce_runlist_id(struct gk20a *g);
 
 u32 gk20a_fifo_get_gr_runlist_id(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 72bf8ea40..22fb96e06 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -53,6 +53,7 @@
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/engines.h>
 #include <nvgpu/engine_status.h>
 
 #include "gr_gk20a.h"
@@ -227,7 +228,7 @@ int gr_gk20a_wait_idle(struct gk20a *g)
 
 	nvgpu_log_fn(g, " ");
 
-	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
+	gr_engine_id = nvgpu_engine_get_gr_eng_id(g);
 
 	nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
@@ -2568,7 +2569,7 @@ void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
 	int ret;
 	u32 engine_id;
 
-	engine_id = gk20a_fifo_get_gr_engine_id(g);
+	engine_id = nvgpu_engine_get_gr_eng_id(g);
 	gr_info = (f->engine_info + engine_id);
 
 	ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
@@ -2911,7 +2912,7 @@ int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr,
 	int ret;
 	u32 engine_id;
 
-	engine_id = gk20a_fifo_get_gr_engine_id(g);
+	engine_id = nvgpu_engine_get_gr_eng_id(g);
 	gr_info = (f->engine_info + engine_id);
 
 	ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
@@ -2961,7 +2962,7 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config)
 
 		/* gr_engine supports both BLCG and ELCG */
 		if ((cgmode == BLCG_MODE) &&
-			(engine_info->engine_enum == ENGINE_GR_GK20A)) {
+			(engine_info->engine_enum == NVGPU_ENGINE_GR_GK20A)) {
 				g->ops.therm.init_blcg_mode(g, mode_config, active_engine_id);
 				break;
 		} else if (cgmode == ELCG_MODE) {
@@ -4743,7 +4744,7 @@ int gk20a_gr_isr(struct gk20a *g)
 		return 0;
 	}
 
-	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
+	gr_engine_id = nvgpu_engine_get_gr_eng_id(g);
 	if (gr_engine_id != FIFO_INVAL_ENGINE_ID) {
 		gr_engine_id = BIT32(gr_engine_id);
 	}
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index ad5680179..70947ef24 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -33,6 +33,7 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/top.h>
+#include <nvgpu/engines.h>
 
 #include "gk20a/fifo_gk20a.h"
 #include "fifo_gm20b.h"
@@ -46,7 +47,7 @@ static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id)
 	u32 fault_id = FIFO_INVAL_MMU_ID;
 	struct fifo_engine_info_gk20a *engine_info;
 
-	engine_info = gk20a_fifo_get_engine_info(g, engine_id);
+	engine_info = nvgpu_engine_get_active_eng_info(g, engine_id);
 
 	if (engine_info != NULL) {
 		fault_id = engine_info->fault_id;
@@ -66,7 +67,7 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
 
 	/* trigger faults for all bad engines */
 	for_each_set_bit(engine_id, &engine_ids, 32UL) {
-		if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) {
+		if (!nvgpu_engine_check_valid_eng_id(g, engine_id)) {
 			nvgpu_err(g, "faulting unknown engine %ld", engine_id);
 		} else {
 			u32 mmu_id = gm20b_engine_id_to_mmu_id(g,
@@ -208,7 +209,7 @@ int gm20b_fifo_init_engine_info(struct fifo_gk20a *f)
 {
 	struct gk20a *g = f->g;
 	int ret = 0;
-	enum fifo_engine engine_enum;
+	enum nvgpu_fifo_engine engine_enum;
 	u32 pbdma_id = U32_MAX;
 	bool found_pbdma_for_runlist = false;
 
@@ -234,7 +235,7 @@ int gm20b_fifo_init_engine_info(struct fifo_gk20a *f)
 			return -EINVAL;
 		}
 
-		engine_enum = gk20a_fifo_engine_enum_from_type(g,
+		engine_enum = nvgpu_engine_enum_from_type(g,
 							dev_info.engine_type);
 
 		info = &g->fifo.engine_info[dev_info.engine_id];
@@ -272,7 +273,7 @@ int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
 	struct gk20a *g = f->g;
 	int ret = 0;
 	u32 i;
-	enum fifo_engine engine_enum;
+	enum nvgpu_fifo_engine engine_enum;
 	u32 pbdma_id = U32_MAX;
 	u32 gr_runlist_id;
 	bool found_pbdma_for_runlist = false;
@@ -309,13 +310,13 @@ int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
 
 			info = &g->fifo.engine_info[dev_info.engine_id];
 
-			engine_enum = gk20a_fifo_engine_enum_from_type(g,
+			engine_enum = nvgpu_engine_enum_from_type(g,
 							dev_info.engine_type);
 
 			/* GR and GR_COPY shares same runlist_id */
-			if ((engine_enum == ENGINE_ASYNC_CE_GK20A) &&
+			if ((engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) &&
 				(gr_runlist_id == dev_info.runlist_id)) {
-					engine_enum = ENGINE_GRCE_GK20A;
+					engine_enum = NVGPU_ENGINE_GRCE_GK20A;
 			}
 			info->engine_enum = engine_enum;
 
@@ -325,7 +326,7 @@ int gm20b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
 			}
 
 			if ((dev_info.fault_id == 0U) &&
-					(engine_enum == ENGINE_GRCE_GK20A)) {
+					(engine_enum == NVGPU_ENGINE_GRCE_GK20A)) {
 				dev_info.fault_id = 0x1b;
 			}
 			info->fault_id = dev_info.fault_id;
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index d2c692a52..44dae2ebc 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -33,6 +33,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/engines.h>
 #include <nvgpu/engine_status.h>
 
 #include "gk20a/gr_gk20a.h"
@@ -915,7 +916,7 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
 	u32 gr_engine_id;
 	struct nvgpu_engine_status_info engine_status;
 
-	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
+	gr_engine_id = nvgpu_engine_get_gr_eng_id(g);
 
 	gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
 		gk20a_readl(g, gr_status_r()));
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index 1b04e495d..b1fec8cbc 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -32,6 +32,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/channel_sync.h>
 #include <nvgpu/channel_sync_syncpt.h>
+#include <nvgpu/engines.h>
 #include <nvgpu/top.h>
 
 #include "fifo_gp10b.h"
@@ -193,7 +194,7 @@ int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
 	struct gk20a *g = f->g;
 	int ret = 0;
 	u32 i;
-	enum fifo_engine engine_enum;
+	enum nvgpu_fifo_engine engine_enum;
 	u32 gr_runlist_id;
 	u32 pbdma_id = U32_MAX;
 	bool found_pbdma_for_runlist = false;
@@ -232,13 +233,13 @@ int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
 
 		info = &g->fifo.engine_info[dev_info.engine_id];
 
-		engine_enum = gk20a_fifo_engine_enum_from_type(
+		engine_enum = nvgpu_engine_enum_from_type(
 					g,
 					dev_info.engine_type);
 		/* GR and GR_COPY shares same runlist_id */
-		if ((engine_enum == ENGINE_ASYNC_CE_GK20A) &&
+		if ((engine_enum == NVGPU_ENGINE_ASYNC_CE_GK20A) &&
 			(gr_runlist_id == dev_info.runlist_id)) {
-				engine_enum = ENGINE_GRCE_GK20A;
+				engine_enum = NVGPU_ENGINE_GRCE_GK20A;
 		}
 		info->engine_enum = engine_enum;
 
@@ -248,7 +249,7 @@ int gp10b_fifo_init_ce_engine_info(struct fifo_gk20a *f)
 		}
 
 		if ((dev_info.fault_id == 0U) &&
-				(engine_enum == ENGINE_GRCE_GK20A)) {
+				(engine_enum == NVGPU_ENGINE_GRCE_GK20A)) {
 			dev_info.fault_id = 0x1b;
 		}
 		info->fault_id = dev_info.fault_id;
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 4bffb30aa..5626cc33b 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -39,6 +39,7 @@
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/ctx.h>
 #include <nvgpu/gr/config.h>
+#include <nvgpu/engines.h>
 #include <nvgpu/engine_status.h>
 
 #include "gk20a/gr_gk20a.h"
@@ -1189,7 +1190,7 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
 	u32 gr_engine_id;
 	struct nvgpu_engine_status_info engine_status;
 
-	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
+	gr_engine_id = nvgpu_engine_get_gr_eng_id(g);
 
 	gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
 		gk20a_readl(g, gr_status_r()));
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index abfe84aa7..5657ae6f8 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -1869,7 +1869,7 @@ static u32 gv11b_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g,
 		active_engine_id = f->active_engines_list[engine_id];
 		engine_info = &g->fifo.engine_info[active_engine_id];
 
-		if (active_engine_id == ENGINE_GR_GK20A) {
+		if (active_engine_id == NVGPU_ENGINE_GR_GK20A) {
 			/* get faulted subctx id */
 			*veid = gv11b_mmu_fault_id_to_gr_veid(g,
 					engine_info->fault_id, mmu_fault_id);
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 1f6f1a317..2e8b85fb1 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -43,6 +43,7 @@
 #include <nvgpu/gr/config.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/nvgpu_err.h>
+#include <nvgpu/engines.h>
 #include <nvgpu/engine_status.h>
 
 #include "gk20a/gr_gk20a.h"
@@ -1949,7 +1950,7 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
 	u32 gr_engine_id;
 	struct nvgpu_engine_status_info engine_status;
 
-	gr_engine_id = gk20a_fifo_get_gr_engine_id(g);
+	gr_engine_id = nvgpu_engine_get_gr_eng_id(g);
 
 	gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
 		gk20a_readl(g, gr_status_r()));
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h
index afcaa0de2..fd714b8f6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h
@@ -416,7 +416,7 @@ struct channel_gk20a *__must_check _gk20a_channel_from_id(struct gk20a *g,
 
 int gk20a_wait_channel_idle(struct channel_gk20a *ch);
 
-/* runlist_id -1 is synonym for ENGINE_GR_GK20A runlist id */
+/* runlist_id -1 is synonym for NVGPU_ENGINE_GR_GK20A runlist id */
 struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
 		s32 runlist_id,
 		bool is_privileged_channel,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h
new file mode 100644
index 000000000..67c588b85
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_ENGINE_H
+#define NVGPU_ENGINE_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct fifo_engine_info_gk20a;
+
+enum nvgpu_fifo_engine {
+	NVGPU_ENGINE_GR_GK20A	       = 0U,
+	NVGPU_ENGINE_GRCE_GK20A      = 1U,
+	NVGPU_ENGINE_ASYNC_CE_GK20A  = 2U,
+	NVGPU_ENGINE_INVAL_GK20A     = 3U,
+};
+
+enum nvgpu_fifo_engine nvgpu_engine_enum_from_type(struct gk20a *g,
+		u32 engine_type);
+
+struct fifo_engine_info_gk20a *nvgpu_engine_get_active_eng_info(
+		struct gk20a *g, u32 engine_id);
+
+u32 nvgpu_engine_get_ids(struct gk20a *g,
+		u32 engine_id[], u32 engine_id_sz,
+		enum nvgpu_fifo_engine engine_enum);
+
+bool nvgpu_engine_check_valid_eng_id(struct gk20a *g, u32 engine_id);
+u32 nvgpu_engine_get_gr_eng_id(struct gk20a *g);
+u32 nvgpu_engine_interrupt_mask(struct gk20a *g);
+u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 act_eng_id);
+u32 nvgpu_engine_get_all_ce_eng_reset_mask(struct gk20a *g);
+
+#endif /*NVGPU_ENGINE_H*/
\ No newline at end of file
diff --git a/drivers/gpu/nvgpu/os/linux/debug_fifo.c b/drivers/gpu/nvgpu/os/linux/debug_fifo.c
index 4567affa2..93349d0eb 100644
--- a/drivers/gpu/nvgpu/os/linux/debug_fifo.c
+++ b/drivers/gpu/nvgpu/os/linux/debug_fifo.c
@@ -22,6 +22,7 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/gr/ctx.h>
+#include <nvgpu/engines.h>
 
 void __gk20a_fifo_profile_free(struct nvgpu_ref *ref);
 
@@ -69,7 +70,7 @@ static int gk20a_fifo_sched_debugfs_seq_show(
 	int ret = SEQ_SKIP;
 	u32 engine_id;
 
-	engine_id = gk20a_fifo_get_gr_engine_id(g);
+	engine_id = nvgpu_engine_get_gr_eng_id(g);
 	engine_info = (f->engine_info + engine_id);
 	runlist_id = engine_info->runlist_id;
 	runlist = &f->runlist_info[runlist_id];
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
index 2f34b8ad3..bcf7754f6 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
@@ -472,7 +472,7 @@ channel_release:
 	return 0;
 }
 
-/* note: runlist_id -1 is synonym for the ENGINE_GR_GK20A runlist id */
+/* note: runlist_id -1 is synonym for the NVGPU_ENGINE_GR_GK20A runlist id */
 static int __gk20a_channel_open(struct gk20a *g,
 				struct file *filp, s32 runlist_id)
 {
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index 033d4ff94..f051e2221 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -882,7 +882,7 @@ static int nvgpu_gpu_get_engine_info(
 	struct nvgpu_gpu_get_engine_info_args *args)
 {
 	int err = 0;
-	u32 engine_enum = ENGINE_INVAL_GK20A;
+	u32 engine_enum = NVGPU_ENGINE_INVAL_GK20A;
 	u32 report_index = 0;
 	u32 engine_id_idx;
 	const u32 max_buffer_engines = args->engine_info_buf_size /
@@ -902,15 +902,15 @@ static int nvgpu_gpu_get_engine_info(
 		engine_enum = src_info->engine_enum;
 
 		switch (engine_enum) {
-		case ENGINE_GR_GK20A:
+		case NVGPU_ENGINE_GR_GK20A:
 			dst_info.engine_id = NVGPU_GPU_ENGINE_ID_GR;
 			break;
 
-		case ENGINE_GRCE_GK20A:
+		case NVGPU_ENGINE_GRCE_GK20A:
 			dst_info.engine_id = NVGPU_GPU_ENGINE_ID_GR_COPY;
 			break;
 
-		case ENGINE_ASYNC_CE_GK20A:
+		case NVGPU_ENGINE_ASYNC_CE_GK20A:
 			dst_info.engine_id = NVGPU_GPU_ENGINE_ID_ASYNC_COPY;
 			break;