gpu: nvgpu: init: add return for all init APIs

This adds return values for all init APIs. This make all the init APIs
have the same signature. This is a prerequisite to making a table of
init functions.

JIRA NVGPU-3980

Change-Id: I5b71fd06ad248092af133ffe908e2930acb6d2b0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202973
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/channel.c

@@ -2635,7 +2635,7 @@ int nvgpu_channel_suspend_all_serviceable_ch(struct gk20a *g)
 	return 0;
 }
 
-void nvgpu_channel_resume_all_serviceable_ch(struct gk20a *g)
+int nvgpu_channel_resume_all_serviceable_ch(struct gk20a *g)
 {
 	struct nvgpu_fifo *f = &g->fifo;
 	u32 chid;
@@ -2668,6 +2668,8 @@ void nvgpu_channel_resume_all_serviceable_ch(struct gk20a *g)
 	}
 
 	nvgpu_log_fn(g, "done");
+
+	return 0;
 }
 
 void nvgpu_channel_semaphore_wakeup(struct gk20a *g, bool post_events)

drivers/gpu/nvgpu/common/init/nvgpu_init.c

@@ -377,9 +377,18 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 		goto done;
 	}
 #endif
-	g->ops.bus.init_hw(g);
 
-	g->ops.priv_ring.enable_priv_ring(g);
+	err = g->ops.bus.init_hw(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init bus HW");
+		goto done;
+	}
+
+	err = g->ops.priv_ring.enable_priv_ring(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init priv_ring");
+		goto done;
+	}
 
 	/* TBD: move this after graphics init in which blcg/slcg is enabled.
 	   This function removes SlowdownOnBoot which applies 32x divider
@@ -458,7 +467,11 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 		}
 	}
 
-	g->ops.mc.intr_enable(g);
+	err = g->ops.mc.intr_enable(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to enable interrupts");
+		goto done;
+	}
 
 	/*
 	 *  Power gate the chip as per the TPC PG mask
@@ -607,7 +620,12 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 	}
 #endif
 
-	g->ops.chip_init_gpu_characteristics(g);
+	err = g->ops.chip_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init chip gpu characteristics");
+		goto done;
+	}
+
 
 #ifdef CONFIG_NVGPU_DEBUGGER
 	/* Restore the debug setting */
@@ -670,7 +688,11 @@ int nvgpu_finalize_poweron(struct gk20a *g)
 #endif
 
 	if (g->ops.channel.resume_all_serviceable_ch != NULL) {
-		g->ops.channel.resume_all_serviceable_ch(g);
+		err = g->ops.channel.resume_all_serviceable_ch(g);
+		if (err != 0) {
+			nvgpu_err(g, "Failed to resume channels");
+			goto done;
+		}
 	}
 
 	goto exit;
@@ -703,7 +725,7 @@ int nvgpu_can_busy(struct gk20a *g)
 	}
 }
 
-void nvgpu_init_gpu_characteristics(struct gk20a *g)
+int nvgpu_init_gpu_characteristics(struct gk20a *g)
 {
 #ifdef NV_BUILD_CONFIGURATION_IS_SAFETY
 	nvgpu_set_enabled(g, NVGPU_DRIVER_REDUCED_PROFILE, true);
@@ -751,6 +773,8 @@ void nvgpu_init_gpu_characteristics(struct gk20a *g)
 		g->ops.gr.init_cyclestats(g);
 	}
 #endif
+
+	return 0;
 }
 
 static struct gk20a *gk20a_from_refcount(struct nvgpu_ref *refcount)

drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.c

@@ -103,11 +103,17 @@ void vgpu_remove_support_common(struct gk20a *g)
 	nvgpu_kfree(g, priv->freqs);
 }
 
-void vgpu_init_gpu_characteristics(struct gk20a *g)
+int vgpu_init_gpu_characteristics(struct gk20a *g)
 {
+	int err;
+
 	nvgpu_log_fn(g, " ");
 
-	nvgpu_init_gpu_characteristics(g);
+	err = nvgpu_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
 
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true);
 
@@ -116,6 +122,8 @@ void vgpu_init_gpu_characteristics(struct gk20a *g)
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, false);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false);
+
+	return 0;
 }
 
 int vgpu_get_constants(struct gk20a *g)
@@ -204,9 +212,17 @@ int vgpu_finalize_poweron_common(struct gk20a *g)
 	}
 #endif
 
-	g->ops.chip_init_gpu_characteristics(g);
+	err = g->ops.chip_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
 
-	g->ops.channel.resume_all_serviceable_ch(g);
+	err = g->ops.channel.resume_all_serviceable_ch(g);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to resume channels");
+		return err;
+	}
 
 	return 0;
 }

drivers/gpu/nvgpu/common/vgpu/init/init_vgpu.h

@@ -27,7 +27,7 @@ struct gk20a;
 
 u64 vgpu_connect(void);
 void vgpu_remove_support_common(struct gk20a *g);
-void vgpu_init_gpu_characteristics(struct gk20a *g);
+int vgpu_init_gpu_characteristics(struct gk20a *g);
 int vgpu_get_constants(struct gk20a *g);
 int vgpu_finalize_poweron_common(struct gk20a *g);
 

drivers/gpu/nvgpu/hal/bus/bus_gk20a.h

@@ -30,7 +30,7 @@ struct nvgpu_sgt;
 struct nvgpu_sgl;
 
 void gk20a_bus_isr(struct gk20a *g);
-void gk20a_bus_init_hw(struct gk20a *g);
+int gk20a_bus_init_hw(struct gk20a *g);
 #ifdef CONFIG_NVGPU_DGPU
 u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem,
 		       struct nvgpu_sgt *sgt,

drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c

@@ -33,7 +33,7 @@
 
 #include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
 
-void gk20a_bus_init_hw(struct gk20a *g)
+int gk20a_bus_init_hw(struct gk20a *g)
 {
 	u32 intr_en_mask = 0;
 
@@ -48,6 +48,8 @@ void gk20a_bus_init_hw(struct gk20a *g)
 	if (g->ops.bus.configure_debug_bus != NULL) {
 		g->ops.bus.configure_debug_bus(g);
 	}
+
+	return 0;
 }
 
 void gk20a_bus_isr(struct gk20a *g)

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -153,11 +153,19 @@
 
 #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
 
-static void gp10b_init_gpu_characteristics(struct gk20a *g)
+static int gp10b_init_gpu_characteristics(struct gk20a *g)
 {
-	nvgpu_init_gpu_characteristics(g);
+	int err;
+
+	err = nvgpu_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
 	g->ops.gr.ecc.detect(g);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
+
+	return 0;
 }
 
 static const struct gpu_ops gp10b_ops = {

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -183,9 +183,16 @@
 
 #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
 
-static void gv11b_init_gpu_characteristics(struct gk20a *g)
+static int gv11b_init_gpu_characteristics(struct gk20a *g)
 {
-	nvgpu_init_gpu_characteristics(g);
+	int err;
+
+	err = nvgpu_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
+
 	g->ops.gr.ecc.detect(g);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
@@ -195,6 +202,8 @@ static void gv11b_init_gpu_characteristics(struct gk20a *g)
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
+
+	return 0;
 }
 
 static const struct gpu_ops gv11b_ops = {

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -219,9 +219,15 @@
 
 #include <nvgpu/hw/tu104/hw_pwr_tu104.h>
 
-static void tu104_init_gpu_characteristics(struct gk20a *g)
+static int tu104_init_gpu_characteristics(struct gk20a *g)
 {
-	nvgpu_init_gpu_characteristics(g);
+	int err;
+
+	err = nvgpu_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
 
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
@@ -231,6 +237,8 @@ static void tu104_init_gpu_characteristics(struct gk20a *g)
 	}
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_USERMODE_SUBMIT, true);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_DEVICE_EVENTS, true);
+
+	return 0;
 }
 
 

drivers/gpu/nvgpu/hal/mc/mc_gm20b.c

@@ -98,7 +98,7 @@ void gm20b_mc_intr_mask(struct gk20a *g)
 		mc_intr_en_1_inta_disabled_f());
 }
 
-void gm20b_mc_intr_enable(struct gk20a *g)
+int gm20b_mc_intr_enable(struct gk20a *g)
 {
 	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
@@ -116,6 +116,8 @@ void gm20b_mc_intr_enable(struct gk20a *g)
 		     | eng_intr_mask);
 	nvgpu_writel(g, mc_intr_en_0_r(),
 		mc_intr_en_0_inta_hardware_f());
+
+	return 0;
 }
 
 void gm20b_mc_intr_pmu_unit_config(struct gk20a *g, bool enable)

drivers/gpu/nvgpu/hal/mc/mc_gm20b.h

@@ -41,7 +41,7 @@ bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
 
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void gm20b_mc_intr_mask(struct gk20a *g);
-void gm20b_mc_intr_enable(struct gk20a *g);
+int gm20b_mc_intr_enable(struct gk20a *g);
 void gm20b_mc_intr_pmu_unit_config(struct gk20a *g, bool enable);
 void gm20b_mc_isr_stall(struct gk20a *g);
 u32  gm20b_mc_intr_stall(struct gk20a *g);

drivers/gpu/nvgpu/hal/mc/mc_gp10b.c

@@ -36,7 +36,7 @@
 
 #include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
 
-void mc_gp10b_intr_enable(struct gk20a *g)
+int mc_gp10b_intr_enable(struct gk20a *g)
 {
 	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
@@ -59,4 +59,6 @@ void mc_gp10b_intr_enable(struct gk20a *g)
 				 eng_intr_mask;
 	nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
 			g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
+
+	return 0;
 }

drivers/gpu/nvgpu/hal/mc/mc_gp10b.h

@@ -46,7 +46,7 @@ void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
 void mc_gp10b_ltc_isr(struct gk20a *g);
 
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
-void mc_gp10b_intr_enable(struct gk20a *g);
+int mc_gp10b_intr_enable(struct gk20a *g);
 #endif
 
 #endif

drivers/gpu/nvgpu/hal/mc/mc_gv100.c

@@ -35,7 +35,7 @@
 
 #include <nvgpu/hw/gv100/hw_mc_gv100.h>
 
-void mc_gv100_intr_enable(struct gk20a *g)
+int mc_gv100_intr_enable(struct gk20a *g)
 {
 	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
@@ -62,6 +62,7 @@ void mc_gv100_intr_enable(struct gk20a *g)
 	nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
 			g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
 
+	return 0;
 }
 
 bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)

drivers/gpu/nvgpu/hal/mc/mc_gv100.h

@@ -27,7 +27,7 @@
 
 struct gk20a;
 
-void mc_gv100_intr_enable(struct gk20a *g);
+int mc_gv100_intr_enable(struct gk20a *g);
 bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0);
 bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
 			u32 *eng_intr_pending);

drivers/gpu/nvgpu/hal/mc/mc_gv11b.h

@@ -27,7 +27,7 @@
 
 struct gk20a;
 
-void mc_gv11b_intr_enable(struct gk20a *g);
+int mc_gv11b_intr_enable(struct gk20a *g);
 bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
 bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
 			u32 *eng_intr_pending);

drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c

@@ -33,7 +33,7 @@
 
 #include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 
-void mc_gv11b_intr_enable(struct gk20a *g)
+int mc_gv11b_intr_enable(struct gk20a *g)
 {
 	u32 eng_intr_mask = nvgpu_engine_interrupt_mask(g);
 
@@ -60,6 +60,7 @@ void mc_gv11b_intr_enable(struct gk20a *g)
 	nvgpu_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
 			g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
 
+	return 0;
 }
 
 bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)

drivers/gpu/nvgpu/hal/mc/mc_tu104.c

@@ -217,10 +217,12 @@ void intr_tu104_mask(struct gk20a *g)
 }
 
 /* Enable all required interrupts */
-void intr_tu104_enable(struct gk20a *g)
+int intr_tu104_enable(struct gk20a *g)
 {
 	intr_tu104_stall_enable(g);
 	intr_tu104_nonstall_enable(g);
+
+	return 0;
 }
 
 /* Return non-zero if nonstall interrupts are pending */

drivers/gpu/nvgpu/hal/mc/mc_tu104.h

@@ -50,7 +50,7 @@ bool intr_tu104_vector_intr_pending(struct gk20a *g, u32 intr_vector);
 void intr_tu104_intr_clear_leaf_vector(struct gk20a *g, u32 intr_vector);
 
 void intr_tu104_mask(struct gk20a *g);
-void intr_tu104_enable(struct gk20a *g);
+int intr_tu104_enable(struct gk20a *g);
 u32  intr_tu104_stall(struct gk20a *g);
 void intr_tu104_stall_pause(struct gk20a *g);
 void intr_tu104_stall_resume(struct gk20a *g);

drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.h

@@ -30,7 +30,7 @@ struct gk20a;
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 void gm20b_priv_ring_isr(struct gk20a *g);
 #endif
-void gm20b_priv_ring_enable(struct gk20a *g);
+int gm20b_priv_ring_enable(struct gk20a *g);
 void gm20b_priv_set_timeout_settings(struct gk20a *g);
 u32 gm20b_priv_ring_enum_ltc(struct gk20a *g);
 

drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b_fusa.c

@@ -36,12 +36,12 @@
 #include <nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h>
 
-void gm20b_priv_ring_enable(struct gk20a *g)
+int gm20b_priv_ring_enable(struct gk20a *g)
 {
 #ifdef CONFIG_NVGPU_SIM
 	if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
 		nvgpu_log_info(g, "priv ring is already enabled");
-		return;
+		return 0;
 	}
 #endif
 
@@ -54,6 +54,8 @@ void gm20b_priv_ring_enable(struct gk20a *g)
 	nvgpu_writel(g, pri_ringstation_sys_decode_config_r(), 0x2);
 
 	(void) nvgpu_readl(g, pri_ringstation_sys_decode_config_r());
+
+	return 0;
 }
 
 void gm20b_priv_set_timeout_settings(struct gk20a *g)

drivers/gpu/nvgpu/hal/ptimer/ptimer_gp10b.c

@@ -27,9 +27,11 @@
 
 #include <nvgpu/hw/gp10b/hw_timer_gp10b.h>
 
-void gp10b_ptimer_config_gr_tick_freq(struct gk20a *g)
+int gp10b_ptimer_config_gr_tick_freq(struct gk20a *g)
 {
 	nvgpu_writel(g, timer_gr_tick_freq_r(),
 		timer_gr_tick_freq_select_f(
 			timer_gr_tick_freq_select_max_f()));
+
+	return 0;
 }

drivers/gpu/nvgpu/hal/ptimer/ptimer_gp10b.h

@@ -26,7 +26,7 @@
 
 struct gk20a;
 
-void gp10b_ptimer_config_gr_tick_freq(struct gk20a *g);
+int gp10b_ptimer_config_gr_tick_freq(struct gk20a *g);
 
 #endif /* CONFIG_NVGPU_DEBUGGER */
 #endif /* PTIMER_GP10B_H */

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -141,11 +141,17 @@
 
 #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
 
-static void vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
+static int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
 {
+	int err;
+
 	nvgpu_log_fn(g, " ");
 
-	vgpu_init_gpu_characteristics(g);
+	err = vgpu_init_gpu_characteristics(g);
+	if (err != 0) {
+		nvgpu_err(g, "failed to init GPU characteristics");
+		return err;
+	}
 
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
 	nvgpu_set_enabled(g, NVGPU_USE_COHERENT_SYSMEM, true);
@@ -160,6 +166,8 @@ static void vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true);
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true);
+
+	return 0;
 }
 
 static const struct gpu_ops vgpu_gv11b_ops = {

drivers/gpu/nvgpu/include/nvgpu/channel.h

@@ -887,8 +887,10 @@ int nvgpu_channel_suspend_all_serviceable_ch(struct gk20a *g);
  * @param g[in]		Pointer to GPU driver struct.
  *
  * Bind all serviceable channels contexts back to hardware.
+ *
+ * @return 0 in case of success, < 0 in case of failure.
  */
-void nvgpu_channel_resume_all_serviceable_ch(struct gk20a *g);
+int nvgpu_channel_resume_all_serviceable_ch(struct gk20a *g);
 
 /**
  * @brief Stop deterministic channel activity for do_idle().

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1365,7 +1365,7 @@ struct gpu_ops {
 #endif
 	struct {
 		void (*intr_mask)(struct gk20a *g);
-		void (*intr_enable)(struct gk20a *g);
+		int (*intr_enable)(struct gk20a *g);
 		void (*intr_pmu_unit_config)(struct gk20a *g,
 				bool enable);
 		void (*isr_stall)(struct gk20a *g);
@@ -1429,10 +1429,10 @@ struct gpu_ops {
 #endif
 
 	u32 (*get_litter_value)(struct gk20a *g, int value);
-	void (*chip_init_gpu_characteristics)(struct gk20a *g);
+	int (*chip_init_gpu_characteristics)(struct gk20a *g);
 
 	struct {
-		void (*init_hw)(struct gk20a *g);
+		int (*init_hw)(struct gk20a *g);
 		void (*isr)(struct gk20a *g);
 		int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
 		int (*bar2_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
@@ -1455,7 +1455,7 @@ struct gpu_ops {
 			struct nvgpu_cpu_time_correlation_sample *samples);
 #endif
 #ifdef CONFIG_NVGPU_DEBUGGER
-		void (*config_gr_tick_freq)(struct gk20a *g);
+		int (*config_gr_tick_freq)(struct gk20a *g);
 #endif
 	} ptimer;
 
@@ -1546,7 +1546,7 @@ struct gpu_ops {
 		int (*fbp_init_support)(struct gk20a *g);
 	} fbp;
 	struct {
-		void (*enable_priv_ring)(struct gk20a *g);
+		int (*enable_priv_ring)(struct gk20a *g);
 		void (*isr)(struct gk20a *g);
 		void (*decode_error_code)(struct gk20a *g, u32 error_code);
 		void (*set_ppriv_timeout_settings)(struct gk20a *g);

drivers/gpu/nvgpu/include/nvgpu/gops_channel.h

@@ -43,7 +43,7 @@ struct gops_channel {
 	void (*force_ctx_reload)(struct nvgpu_channel *ch);
 	void (*abort_clean_up)(struct nvgpu_channel *ch);
 	int (*suspend_all_serviceable_ch)(struct gk20a *g);
-	void (*resume_all_serviceable_ch)(struct gk20a *g);
+	int (*resume_all_serviceable_ch)(struct gk20a *g);
 	void (*set_error_notifier)(struct nvgpu_channel *ch, u32 error);
 	void (*reset_faulted)(struct gk20a *g, struct nvgpu_channel *ch,
 			bool eng, bool pbdma);

drivers/gpu/nvgpu/include/nvgpu/nvgpu_init.h

@@ -189,8 +189,10 @@ void nvgpu_check_gpu_state(struct gk20a *g);
  * @param g [in] The GPU
  *
  * This is called during HAL initialization.
+ *
+ * @return 0 in case of success, < 0 in case of failure.
  */
-void nvgpu_init_gpu_characteristics(struct gk20a *g);
+int nvgpu_init_gpu_characteristics(struct gk20a *g);
 
 /**
  * @brief Takes a reference for keeping gpu busy but not try to initialize it.

drivers/gpu/nvgpu/os/linux/debug.c

@@ -199,6 +199,7 @@ static ssize_t disable_bigpage_write(struct file *file, const char __user *user_
 	int buf_size;
 	bool bv;
 	struct gk20a *g = file->private_data;
+	int err;
 
 	buf_size = min(count, (sizeof(buf)-1));
 	if (copy_from_user(buf, user_buf, buf_size))
@@ -206,7 +207,11 @@ static ssize_t disable_bigpage_write(struct file *file, const char __user *user_
 
 	if (strtobool(buf, &bv) == 0) {
 		g->mm.disable_bigpage = bv;
-		nvgpu_init_gpu_characteristics(g);
+		err = nvgpu_init_gpu_characteristics(g);
+		if (err != 0) {
+			nvgpu_err(g, "failed to init GPU characteristics");
+			return -ENOSYS;
+		}
 	}
 
 	return count;

drivers/gpu/nvgpu/os/posix/gk20a.c

@@ -23,9 +23,10 @@
 #include <nvgpu/gk20a.h>
 #include <nvgpu/enabled.h>
 
-void nvgpu_init_gpu_characteristics(struct gk20a *g)
+int nvgpu_init_gpu_characteristics(struct gk20a *g)
 {
 	BUG();
+	return -1;
 }
 
 struct gk20a * __must_check nvgpu_get(struct gk20a *g)