diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
index cef5ad131..b967f6a11 100644
--- a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
+++ b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -77,9 +77,14 @@ static int rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
 			prppg_cmd->stats_reset.ctrl_id;
 		break;
 	default:
-		nvgpu_err(g, "Inivalid RPPG command %d",
+		nvgpu_err(g, "Invalid RPPG command %d",
 			prppg_cmd->cmn.cmd_id);
-		return -1;
+		status = -1;
+		break;
+	}
+
+	if (status != 0) {
+		goto exit;
 	}
 
 	status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
index b1450b69b..a9b449f20 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -47,6 +47,7 @@ static u8 get_perfmon_id(struct nvgpu_pmu *pmu)
 		unit_id = PMU_UNIT_INVALID;
 		nvgpu_err(g, "no support for %x", ver);
 		WARN_ON(true);
+		break;
 	}
 
 	return unit_id;
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
index 1d66af1c8..3a81e21f3 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -108,6 +108,7 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg,
 	default:
 		nvgpu_err(g,
 			"unsupported ELPG message : 0x%04x", elpg_msg->msg);
+		break;
 	}
 }
 
@@ -735,7 +736,12 @@ int nvgpu_pmu_ap_send_command(struct gk20a *g,
 	default:
 		nvgpu_pmu_dbg(g, "%s: Invalid Adaptive Power command %d\n",
 			__func__, p_ap_cmd->cmn.cmd_id);
-		return 0x2f;
+		status = 0x2f;
+		break;
+	}
+
+	if (status != 0) {
+		goto err_return;
 	}
 
 	status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,