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gpu: nvgpu: remove whitelisting for wrongly reported violations by tool

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- Earlier we whitelisted wrongly reported static analysis violations
  by tool, raised coverity tool bugs for these cases.

- These bugs are fixed with new version of tool, so no need fo whitelisting.

JIRA NVGPU-7119

Change-Id: Ib2341db0d46fa7fac4c0cc9a6c1bdc8704377ef1
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2604365
(cherry picked from commit dc2d8ddaa409aefe0e04e0bacb3a8a977f6dbd64)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2677523
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
srajum
2021-10-02 17:24:27 +05:30
committed by mobile promotions
parent 2ff9f6b759
commit 069fe05dca
10 changed files with 0 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -93,14 +93,8 @@ static struct nvgpu_channel *allocate_channel(struct nvgpu_fifo *f)
ch = nvgpu_list_first_entry(&f->free_chs, nvgpu_channel, ch = nvgpu_list_first_entry(&f->free_chs, nvgpu_channel,
free_chs); free_chs);
nvgpu_list_del(&ch->free_chs); nvgpu_list_del(&ch->free_chs);
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(nvgpu_atomic_read(&ch->ref_count) != 0); WARN_ON(nvgpu_atomic_read(&ch->ref_count) != 0);
WARN_ON(ch->referenceable); WARN_ON(ch->referenceable);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
f->used_channels = nvgpu_safe_add_u32(f->used_channels, 1U); f->used_channels = nvgpu_safe_add_u32(f->used_channels, 1U);
} }
nvgpu_mutex_release(&f->free_chs_mutex); nvgpu_mutex_release(&f->free_chs_mutex);
@@ -1200,18 +1194,12 @@ void nvgpu_channel_put__func(struct nvgpu_channel *ch, const char *caller)
/* More puts than gets. Channel is probably going to get /* More puts than gets. Channel is probably going to get
* stuck. */ * stuck. */
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(nvgpu_atomic_read(&ch->ref_count) < 0); WARN_ON(nvgpu_atomic_read(&ch->ref_count) < 0);
/* Also, more puts than gets. ref_count can go to 0 only if /* Also, more puts than gets. ref_count can go to 0 only if
* the channel is closing. Channel is probably going to get * the channel is closing. Channel is probably going to get
* stuck. */ * stuck. */
WARN_ON((nvgpu_atomic_read(&ch->ref_count) == 0) && ch->referenceable); WARN_ON((nvgpu_atomic_read(&ch->ref_count) == 0) && ch->referenceable);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
} }
struct nvgpu_channel *nvgpu_channel_from_id__func(struct gk20a *g, struct nvgpu_channel *nvgpu_channel_from_id__func(struct gk20a *g,
@@ -1265,11 +1253,7 @@ struct nvgpu_channel *nvgpu_channel_open_new(struct gk20a *g,
trace_nvgpu_channel_open_new(ch->chid); trace_nvgpu_channel_open_new(ch->chid);
#endif #endif
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(ch->g != NULL); BUG_ON(ch->g != NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
ch->g = g; ch->g = g;
/* Runlist for the channel */ /* Runlist for the channel */

6
drivers/gpu/nvgpu/common/fifo/runlist.c
View File

@@ -391,13 +391,7 @@ static int nvgpu_runlist_reconstruct_locked(struct gk20a *g,
} }
domain->mem->count = num_entries; domain->mem->count = num_entries;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(domain->mem->count > f->num_runlist_entries); WARN_ON(domain->mem->count > f->num_runlist_entries);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
return 0; return 0;
} }

6
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -1126,13 +1126,7 @@ void nvgpu_tsg_abort(struct gk20a *g, struct nvgpu_tsg *tsg, bool preempt)
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(tsg->abortable == false); WARN_ON(tsg->abortable == false);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
g->ops.tsg.disable(tsg); g->ops.tsg.disable(tsg);

3
drivers/gpu/nvgpu/common/mm/allocators/bitmap_allocator.c
View File

@@ -97,7 +97,6 @@ static u64 nvgpu_bitmap_balloc_fixed(struct nvgpu_allocator *na,
a->bytes_alloced = nvgpu_safe_add_u64(a->bytes_alloced, a->bytes_alloced = nvgpu_safe_add_u64(a->bytes_alloced,
nvgpu_safe_mult_u64(blks, a->blk_size)); nvgpu_safe_mult_u64(blks, a->blk_size));
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_3), "Bug 2615925")
nvgpu_assert(a->nr_fixed_allocs < U64_MAX); nvgpu_assert(a->nr_fixed_allocs < U64_MAX);
a->nr_fixed_allocs++; a->nr_fixed_allocs++;
alloc_unlock(na); alloc_unlock(na);
@@ -396,9 +395,7 @@ static void nvgpu_bitmap_print_stats(struct nvgpu_allocator *na,
} }
#endif #endif
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 8_7), "Bug 2823817")
static const struct nvgpu_allocator_ops bitmap_ops = { static const struct nvgpu_allocator_ops bitmap_ops = {
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.alloc = nvgpu_bitmap_balloc, .alloc = nvgpu_bitmap_balloc,
.free_alloc = nvgpu_bitmap_free, .free_alloc = nvgpu_bitmap_free,

16
drivers/gpu/nvgpu/common/mm/allocators/buddy_allocator.c
View File

@@ -116,13 +116,7 @@ static void balloc_compute_max_order(struct nvgpu_buddy_allocator *a)
static void balloc_allocator_align(struct nvgpu_buddy_allocator *a) static void balloc_allocator_align(struct nvgpu_buddy_allocator *a)
{ {
a->start = NVGPU_ALIGN(a->base, a->blk_size); a->start = NVGPU_ALIGN(a->base, a->blk_size);
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(a->start != a->base); WARN_ON(a->start != a->base);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
nvgpu_assert(a->blk_size > 0ULL); nvgpu_assert(a->blk_size > 0ULL);
a->end = nvgpu_safe_add_u64(a->base, a->length) & a->end = nvgpu_safe_add_u64(a->base, a->length) &
~(a->blk_size - 1U); ~(a->blk_size - 1U);
@@ -336,11 +330,7 @@ static void nvgpu_buddy_allocator_destroy(struct nvgpu_allocator *na)
* Now clean up the unallocated buddies. * Now clean up the unallocated buddies.
*/ */
for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) { for (i = 0U; i < GPU_BALLOC_ORDER_LIST_LEN; i++) {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(a->buddy_list_alloced[i] != 0U); BUG_ON(a->buddy_list_alloced[i] != 0U);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
while (!nvgpu_list_empty(balloc_get_order_list(a, i))) { while (!nvgpu_list_empty(balloc_get_order_list(a, i))) {
bud = nvgpu_list_first_entry( bud = nvgpu_list_first_entry(
@@ -794,11 +784,7 @@ static u64 balloc_do_alloc_fixed(struct nvgpu_buddy_allocator *a,
* in the lists that hold buddies. This leads to some very strange * in the lists that hold buddies. This leads to some very strange
* crashes. * crashes.
*/ */
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(pte_size == BALLOC_PTE_SIZE_INVALID); BUG_ON(pte_size == BALLOC_PTE_SIZE_INVALID);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
shifted_base = balloc_base_shift(a, base); shifted_base = balloc_base_shift(a, base);
if (shifted_base == 0U) { if (shifted_base == 0U) {
@@ -1365,9 +1351,7 @@ static void nvgpu_buddy_print_stats(struct nvgpu_allocator *na,
} }
#endif #endif
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 8_7), "Bug 2823817")
static const struct nvgpu_allocator_ops buddy_ops = { static const struct nvgpu_allocator_ops buddy_ops = {
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.alloc = nvgpu_buddy_balloc, .alloc = nvgpu_buddy_balloc,
.alloc_pte = nvgpu_buddy_balloc_pte, .alloc_pte = nvgpu_buddy_balloc_pte,
.free_alloc = nvgpu_buddy_bfree, .free_alloc = nvgpu_buddy_bfree,

62
drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
View File

@@ -110,13 +110,7 @@ u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u64 w)
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u32 *ptr = mem->cpu_va; u32 *ptr = mem->cpu_va;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(ptr == NULL); WARN_ON(ptr == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
data = ptr[w]; data = ptr[w];
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -142,38 +136,20 @@ u64 nvgpu_mem_rd32_pair(struct gk20a *g, struct nvgpu_mem *mem, u32 lo, u32 hi)
u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u64 offset) u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u64 offset)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
return nvgpu_mem_rd32(g, mem, offset / (u64)sizeof(u32)); return nvgpu_mem_rd32(g, mem, offset / (u64)sizeof(u32));
} }
void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem,
u64 offset, void *dest, u64 size) u64 offset, void *dest, u64 size)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
WARN_ON((size & 3ULL) != 0ULL); WARN_ON((size & 3ULL) != 0ULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u8 *src = (u8 *)mem->cpu_va + offset; u8 *src = (u8 *)mem->cpu_va + offset;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(mem->cpu_va == NULL); WARN_ON(mem->cpu_va == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
nvgpu_memcpy((u8 *)dest, src, size); nvgpu_memcpy((u8 *)dest, src, size);
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -191,13 +167,7 @@ void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u64 w, u32 data)
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u32 *ptr = mem->cpu_va; u32 *ptr = mem->cpu_va;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(ptr == NULL); WARN_ON(ptr == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
ptr[w] = data; ptr[w] = data;
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -217,38 +187,20 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, u32 data) void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, u32 data)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
nvgpu_mem_wr32(g, mem, offset / (u64)sizeof(u32), data); nvgpu_mem_wr32(g, mem, offset / (u64)sizeof(u32), data);
} }
void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u64 offset,
void *src, u64 size) void *src, u64 size)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 2, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
WARN_ON((size & 3ULL) != 0ULL); WARN_ON((size & 3ULL) != 0ULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u8 *dest = (u8 *)mem->cpu_va + offset; u8 *dest = (u8 *)mem->cpu_va + offset;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(mem->cpu_va == NULL); WARN_ON(mem->cpu_va == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
nvgpu_memcpy(dest, (u8 *)src, size); nvgpu_memcpy(dest, (u8 *)src, size);
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -267,28 +219,16 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u64 offset, void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u64 offset,
u32 c, u64 size) u32 c, u64 size)
{ {
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 3, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 3, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 3, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON((offset & 3ULL) != 0ULL); WARN_ON((offset & 3ULL) != 0ULL);
WARN_ON((size & 3ULL) != 0ULL); WARN_ON((size & 3ULL) != 0ULL);
WARN_ON((c & ~0xffU) != 0U); WARN_ON((c & ~0xffU) != 0U);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
c &= 0xffU; c &= 0xffU;
if (mem->aperture == APERTURE_SYSMEM) { if (mem->aperture == APERTURE_SYSMEM) {
u8 *dest = (u8 *)mem->cpu_va + offset; u8 *dest = (u8 *)mem->cpu_va + offset;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(mem->cpu_va == NULL); WARN_ON(mem->cpu_va == NULL);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
(void) memset(dest, (int)c, size); (void) memset(dest, (int)c, size);
} }
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
@@ -367,9 +307,7 @@ static void nvgpu_mem_phys_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt)
*/ */
} }
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 8_7), "Bug 2823817")
static const struct nvgpu_sgt_ops nvgpu_mem_phys_ops = { static const struct nvgpu_sgt_ops nvgpu_mem_phys_ops = {
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.sgl_next = nvgpu_mem_phys_sgl_next, .sgl_next = nvgpu_mem_phys_sgl_next,
.sgl_dma = nvgpu_mem_phys_sgl_dma, .sgl_dma = nvgpu_mem_phys_sgl_dma,
.sgl_phys = nvgpu_mem_phys_sgl_phys, .sgl_phys = nvgpu_mem_phys_sgl_phys,

6
drivers/gpu/nvgpu/common/mm/vm.c
View File

@@ -289,13 +289,7 @@ void nvgpu_vm_mapping_batch_finish_locked(
int err; int err;
/* hanging kref_put batch pointer? */ /* hanging kref_put batch pointer? */
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(vm->kref_put_batch == mapping_batch); WARN_ON(vm->kref_put_batch == mapping_batch);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
if (mapping_batch->need_tlb_invalidate) { if (mapping_batch->need_tlb_invalidate) {
struct gk20a *g = gk20a_from_vm(vm); struct gk20a *g = gk20a_from_vm(vm);

6
drivers/gpu/nvgpu/hal/fifo/runlist_ram_gv11b_fusa.c
View File

@@ -50,13 +50,7 @@ void gv11b_runlist_get_tsg_entry(struct nvgpu_tsg *tsg,
u32 timeout = timeslice; u32 timeout = timeslice;
u32 scale = 0U; u32 scale = 0U;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 10_3), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
WARN_ON(timeslice == 0U); WARN_ON(timeslice == 0U);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 10_3))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
while (timeout > RL_MAX_TIMESLICE_TIMEOUT) { while (timeout > RL_MAX_TIMESLICE_TIMEOUT) {
timeout >>= 1U; timeout >>= 1U;

4
drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
View File

@@ -151,11 +151,7 @@ void gm20b_gr_falcon_bind_instblk(struct gk20a *g,
nvgpu_writel(g, gr_fecs_arb_ctx_adr_r(), 0x0); nvgpu_writel(g, gr_fecs_arb_ctx_adr_r(), 0x0);
inst_ptr >>= 12; inst_ptr >>= 12;
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 14_4), "Bug 2277532")
NVGPU_COV_WHITELIST_BLOCK_BEGIN(false_positive, 1, NVGPU_MISRA(Rule, 15_6), "Bug 2277532")
BUG_ON(u64_hi32(inst_ptr) != 0U); BUG_ON(u64_hi32(inst_ptr) != 0U);
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 14_4))
NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 15_6))
inst_ptr_u32 = (u32)inst_ptr; inst_ptr_u32 = (u32)inst_ptr;
nvgpu_writel(g, gr_fecs_new_ctx_r(), nvgpu_writel(g, gr_fecs_new_ctx_r(),
gr_fecs_new_ctx_ptr_f(inst_ptr_u32) | gr_fecs_new_ctx_ptr_f(inst_ptr_u32) |

1
drivers/gpu/nvgpu/os/posix/bitmap.c
View File

@@ -51,7 +51,6 @@ unsigned long nvgpu_posix_ffs(unsigned long word)
nvgpu_safe_cast_u64_to_s64( nvgpu_safe_cast_u64_to_s64(
(word & (unsigned long) LONG_MAX))); (word & (unsigned long) LONG_MAX)));
} else { } else {
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_3), "Bug 2615925")
if (word > (unsigned long) LONG_MAX) { if (word > (unsigned long) LONG_MAX) {
ret = maxvalue; ret = maxvalue;
} }