diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index 86a62db22..84b1851dd 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -145,13 +145,20 @@ u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc)
 
 u32 nvgpu_gr_sm_offset(struct gk20a *g, u32 sm)
 {
-
 	u32 sm_pri_stride = nvgpu_get_litter_value(g, GPU_LIT_SM_PRI_STRIDE);
 	u32 sm_offset = nvgpu_safe_mult_u32(sm_pri_stride, sm);
 
 	return sm_offset;
 }
 
+u32 nvgpu_gr_rop_offset(struct gk20a *g, u32 rop)
+{
+	u32 rop_pri_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE);
+	u32 rop_offset = nvgpu_safe_mult_u32(rop_pri_stride, rop);
+
+	return rop_offset;
+}
+
 void nvgpu_gr_init(struct gk20a *g)
 {
 	(void)nvgpu_cond_init(&g->gr->init_wq);
diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr.c b/drivers/gpu/nvgpu/common/gr/gr_intr.c
index f44a7905d..c7fcd773d 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_intr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr_intr.c
@@ -705,6 +705,24 @@ int nvgpu_gr_intr_handle_gpc_exception(struct gk20a *g, bool *post_event,
 				gpc_exception);
 		}
 
+		/* Handle ZROP exception */
+		if (g->ops.gr.intr.handle_gpc_zrop_hww != NULL) {
+			 g->ops.gr.intr.handle_gpc_zrop_hww(g, gpc,
+				gpc_exception);
+		}
+
+		/* Handle CROP exception */
+		if (g->ops.gr.intr.handle_gpc_crop_hww != NULL) {
+			 g->ops.gr.intr.handle_gpc_crop_hww(g, gpc,
+				gpc_exception);
+		}
+
+		/* Handle RRH exception */
+		if (g->ops.gr.intr.handle_gpc_rrh_hww != NULL) {
+			 g->ops.gr.intr.handle_gpc_rrh_hww(g, gpc,
+				gpc_exception);
+		}
+
 	}
 
 	return ret;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
index 874fe953a..07b89c897 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
@@ -457,6 +457,12 @@ struct gops_gr_intr {
 				struct nvgpu_gr_isr_data *isr_data);
 	void (*handle_notify_pending)(struct gk20a *g,
 				struct nvgpu_gr_isr_data *isr_data);
+	void (*handle_gpc_zrop_hww)(struct gk20a *g, u32 gpc,
+			u32 gpc_exception);
+	void (*handle_gpc_crop_hww)(struct gk20a *g, u32 gpc,
+			u32 gpc_exception);
+	void (*handle_gpc_rrh_hww)(struct gk20a *g, u32 gpc,
+			u32 gpc_exception);
 	void (*handle_gcc_exception)(struct gk20a *g, u32 gpc,
 			u32 gpc_exception,
 			u32 *corrected_err, u32 *uncorrected_err);
@@ -485,6 +491,8 @@ struct gops_gr_intr {
 	void (*enable_exceptions)(struct gk20a *g,
 				  struct nvgpu_gr_config *gr_config,
 				  bool enable);
+	void (*enable_gpc_crop_hww)(struct gk20a *g);
+	void (*enable_gpc_zrop_hww)(struct gk20a *g);
 	void (*enable_gpc_exceptions)(struct gk20a *g,
 				struct nvgpu_gr_config *gr_config);
 	void (*tpc_exception_sm_enable)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
index 4582c4cdc..7f80e9713 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
@@ -318,6 +318,19 @@ u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc);
  */
 u32 nvgpu_gr_sm_offset(struct gk20a *g, u32 sm);
 
+/**
+ * @brief Get pri base register offset of a given ROP instance within a GPC
+ *
+ * @param g [in]	Pointer to GPU driver struct.
+ * @param rop [in]	ROP index.
+ *
+ * This function calculates and returns base register offset of a given
+ * ROP within a GPC.
+ *
+ * @return base register offset of a given ROP.
+ */
+u32 nvgpu_gr_rop_offset(struct gk20a *g, u32 rop);
+
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 /**
  * @brief Wait for GR engine to be initialized