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gpu: nvgpu: mmu_fault_id for ce mmu fault handling

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gv11b_mm_mmu_fault_handle_mmu_fault_common was calling
gv11b_mm_mmu_fault_handle_mmu_fault_ce for any mmu_engine_id
greater than gmmu_fault_mmu_eng_id_ce0_v().
This include GR engine on gv11b.

Check the range of mmu_fault_id for CEs instead, before
calling gv11b_mm_mmu_fault_handle_mmu_fault_ce.

Jira NVGPU-4511

Change-Id: I28a78872918dc97e0878ef4c116059eaf5d7fa7b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264975
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-12-18 13:18:59 -05:00
committed by Alex Waterman
parent 5856b230fb
commit 07a0fe707f
1 changed files with 25 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

53
drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c
View File

@@ -291,43 +291,39 @@ static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
}
static bool gv11b_mm_mmu_fault_handle_mmu_fault_ce(struct gk20a *g,
struct mmu_fault_info *mmufault, u32 *invalidate_replay_val,
u32 num_lce)
struct mmu_fault_info *mmufault, u32 *invalidate_replay_val)
{
struct nvgpu_tsg *tsg = NULL;
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
int err;
#endif
if (mmufault->mmu_engine_id <
nvgpu_safe_add_u32(gmmu_fault_mmu_eng_id_ce0_v(),
num_lce)) {
/* CE page faults are not reported as replayable */
nvgpu_log(g, gpu_dbg_intr, "CE Faulted");
/* CE page faults are not reported as replayable */
nvgpu_log(g, gpu_dbg_intr, "CE Faulted");
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
err = gv11b_fb_fix_page_fault(g, mmufault);
err = gv11b_fb_fix_page_fault(g, mmufault);
#endif
if (mmufault->refch != NULL) {
tsg = nvgpu_tsg_from_ch(mmufault->refch);
nvgpu_tsg_reset_faulted_eng_pbdma(g, tsg, true, true);
}
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
if (err == 0) {
*invalidate_replay_val = 0;
nvgpu_log(g, gpu_dbg_intr, "CE Page Fault Fixed");
if (mmufault->refch != NULL) {
tsg = nvgpu_tsg_from_ch(mmufault->refch);
nvgpu_tsg_reset_faulted_eng_pbdma(g, tsg,
true, true);
nvgpu_channel_put(mmufault->refch);
mmufault->refch = NULL;
}
#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
if (err == 0) {
*invalidate_replay_val = 0;
nvgpu_log(g, gpu_dbg_intr, "CE Page Fault Fixed");
if (mmufault->refch != NULL) {
nvgpu_channel_put(mmufault->refch);
mmufault->refch = NULL;
}
return true;
}
#endif
/* Do recovery */
nvgpu_log(g, gpu_dbg_intr, "CE Page Fault Not Fixed");
return true;
}
#endif
/* Do recovery */
nvgpu_log(g, gpu_dbg_intr, "CE Page Fault Not Fixed");
return false;
}
@@ -459,10 +455,11 @@ void gv11b_mm_mmu_fault_handle_mmu_fault_common(struct gk20a *g,
}
num_lce = g->ops.top.get_num_lce(g);
if (mmufault->mmu_engine_id >=
gmmu_fault_mmu_eng_id_ce0_v()) {
if ((mmufault->mmu_engine_id >= gmmu_fault_mmu_eng_id_ce0_v()) &&
(mmufault->mmu_engine_id <
nvgpu_safe_add_u32(gmmu_fault_mmu_eng_id_ce0_v(), num_lce))) {
ret = gv11b_mm_mmu_fault_handle_mmu_fault_ce(g, mmufault,
invalidate_replay_val, num_lce);
invalidate_replay_val);
if (ret) {
return;
}