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nvgpu:Added PROD settings for ELPG sequencing

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Added PROD settings for ELPG sequencing registers

Bug 200023161

Change-Id: Id313f9bc800d3a57f45aff0f0f609887565971be
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2014-07-24 10:26:58 +05:30
committed by Dan Willemsen
parent e5f82c848d
commit 0858498f7b
4 changed files with 142 additions and 1 deletions
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1
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -238,6 +238,7 @@ struct gpu_ops {
struct { struct {
int (*prepare_ucode)(struct gk20a *g); int (*prepare_ucode)(struct gk20a *g);
int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g);
int (*pmu_setup_elpg)(struct gk20a *g);
} pmu; } pmu;
struct { struct {
int (*init_clk_support)(struct gk20a *g); int (*init_clk_support)(struct gk20a *g);

7
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
View File

@@ -2280,8 +2280,12 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g)
/* Save zbc table after PMU is initialized. */ /* Save zbc table after PMU is initialized. */
gr_gk20a_pmu_save_zbc(g, 0xf); gr_gk20a_pmu_save_zbc(g, 0xf);
if (g->elpg_enabled) if (g->elpg_enabled) {
/* Init reg with prod values*/
if (g->ops.pmu.pmu_setup_elpg)
g->ops.pmu.pmu_setup_elpg(g);
gk20a_pmu_enable_elpg(g); gk20a_pmu_enable_elpg(g);
}
udelay(50); udelay(50);
@@ -2296,6 +2300,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
{ {
gops->pmu.prepare_ucode = gk20a_prepare_ucode; gops->pmu.prepare_ucode = gk20a_prepare_ucode;
gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
gops->pmu.pmu_setup_elpg = NULL;
} }
int gk20a_init_pmu_support(struct gk20a *g) int gk20a_init_pmu_support(struct gk20a *g)

133
drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
View File

@@ -15,6 +15,138 @@
#include "gk20a/gk20a.h" #include "gk20a/gk20a.h"
#include "acr_gm20b.h" #include "acr_gm20b.h"
#include "pmu_gm20b.h"
/*!
* Structure/object which single register write need to be done during PG init
* sequence to set PROD values.
*/
struct pg_init_sequence_list {
u32 regaddr;
u32 writeval;
};
/* PROD settings for ELPG sequencing registers*/
static struct pg_init_sequence_list _pginitseq_gm20b[] = {
{ 0x0010ab10, 0x8180},
{ 0x0010e118, 0x81818080},
{ 0x0010e068, 0},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000082},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000082},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000082},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000082},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000082},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000082},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000083},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000080},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000081},
{ 0x0010e06c, 0x00000082},
{ 0x0010e06c, 0x00000083},
{ 0x0010ab14, 0x00000000},
{ 0x0010ab18, 0x00000000},
{ 0x0010e024, 0x00000000},
{ 0x0010e028, 0x00000000},
{ 0x0010e11c, 0x00000000},
{ 0x0010e120, 0x00000000},
{ 0x0010ab1c, 0x00010011},
{ 0x0010e020, 0x001C0011},
{ 0x0010e124, 0x00030011},
{ 0x0010ab20, 0xfedcba98},
{ 0x0010ab24, 0x00000000},
{ 0x0010e02c, 0xfedcba98},
{ 0x0010e030, 0x00000000},
{ 0x0010e128, 0xfedcba98},
{ 0x0010e12c, 0x00000000},
{ 0x0010ab28, 0x71111111},
{ 0x0010ab2c, 0x70000000},
{ 0x0010e034, 0x71111111},
{ 0x0010e038, 0x70000000},
{ 0x0010e130, 0x71111111},
{ 0x0010e134, 0x70000000},
{ 0x0010ab30, 0x00000000},
{ 0x0010ab34, 0x00000001},
{ 0x00020004, 0x00000000},
{ 0x0010e138, 0x00000000},
{ 0x0010e040, 0x00000000},
};
int gm20b_pmu_setup_elpg(struct gk20a *g)
{
int ret = 0;
u32 reg_writes;
u32 index;
gk20a_dbg_fn("");
if (g->elpg_enabled) {
reg_writes = ((sizeof(_pginitseq_gm20b) /
sizeof((_pginitseq_gm20b)[0])));
/* Initialize registers with production values*/
for (index = 0; index < reg_writes; index++) {
gk20a_writel(g, _pginitseq_gm20b[index].regaddr,
_pginitseq_gm20b[index].writeval);
}
}
gk20a_dbg_fn("done");
return ret;
}
void gm20b_init_pmu_ops(struct gpu_ops *gops) void gm20b_init_pmu_ops(struct gpu_ops *gops)
{ {
@@ -23,4 +155,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops)
#else #else
gk20a_init_pmu_ops(gops); gk20a_init_pmu_ops(gops);
#endif #endif
gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg;
} }

2
drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
View File

@@ -15,5 +15,7 @@
#ifndef __PMU_GM20B_H_ #ifndef __PMU_GM20B_H_
#define __PMU_GM20B_H_ #define __PMU_GM20B_H_
void gm20b_init_pmu_ops(struct gpu_ops *gops); void gm20b_init_pmu_ops(struct gpu_ops *gops);
#endif /*__PMU_GM20B_H_*/ #endif /*__PMU_GM20B_H_*/