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gpu: nvgpu: rmmod support in dgpu simulation

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Changes added to support "rmmod nvgpu" in dgpu simulation after gpu
poweron.

nvgpu_engine-wait_for_idle got stuck in busy mode for nvdec and nvec
engines in simulation as simulation doesnt support timeout.
These engines are not valid engines in nvgpu engine list.
Add nvgpu_engine_check_valid_id before checking engine status.

Simulation crash on accessing 0xb81604 top interrupt register.
Add func_priv_cpu_intr_top__size_1_v() function to get the supported
size than using default MAX_INTR_TOP_REGS.

nvlink is not supprted in dgpu simulation. Avoid warning for
-ENODEV return.

Avoid register read following gpu power off completion.

Bug 2498574

Change-Id: I9f9f1cf1ac4620242bda1d2cc0f29f51f81a6711
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2179930
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2019-08-20 23:58:23 -07:00
committed by mobile promotions
parent d93e82dedb
commit 087d4d3df4
6 changed files with 17 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/hal/mc/mc_tu104.c
View File

@@ -367,7 +367,7 @@ void intr_tu104_stall_resume(struct gk20a *g)
void intr_tu104_log_pending_intrs(struct gk20a *g)
{
bool pending;
u32 intr, i;
u32 intr, i, size;
intr = intr_tu104_nonstall(g);
if (intr != 0U) {
@@ -386,7 +386,8 @@ void intr_tu104_log_pending_intrs(struct gk20a *g)
}
}
for (i = 0U; i < MAX_INTR_TOP_REGS; i++) {
size = func_priv_cpu_intr_top__size_1_v();
for (i = 0U; i < size; i++) {
intr = nvgpu_func_readl(g,
func_priv_cpu_intr_top_r(i));
if (intr == 0U) {

2
drivers/gpu/nvgpu/hal/mc/mc_tu104.h
View File

@@ -25,8 +25,6 @@
#include <nvgpu/types.h>
#define MAX_INTR_TOP_REGS (2U)
#define NV_CPU_INTR_SUBTREE_TO_TOP_IDX(i) ((i) / 32U)
#define NV_CPU_INTR_SUBTREE_TO_TOP_BIT(i) ((i) % 32U)
#define NV_CPU_INTR_SUBTREE_TO_LEAF_REG0(i) ((i)*2U)