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gpu: nvgpu: remove clock domain aliases

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Remove MCLK and GPCCLK domain aliases, now that userspace
has swithed to new enumerations.

Jira DNVGPU-211

Change-Id: I2af2fd67dbed47088d7161ba0605e13dd7c674a5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1292609
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
This commit is contained in:
Thomas Fleury
2017-01-20 17:40:11 -08:00
committed by mobile promotions
parent 0a3e5941ff
commit 09504cdbc3
3 changed files with 4 additions and 26 deletions
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18
drivers/gpu/nvgpu/clk/clk_arb.c
View File

@@ -1628,12 +1628,10 @@ int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
switch (api_domain) { switch (api_domain) {
case NVGPU_GPU_CLK_DOMAIN_MCLK: case NVGPU_GPU_CLK_DOMAIN_MCLK:
case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
dev->mclk_target_mhz = target_mhz; dev->mclk_target_mhz = target_mhz;
break; break;
case NVGPU_GPU_CLK_DOMAIN_GPCCLK: case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
dev->gpc2clk_target_mhz = target_mhz * 2ULL; dev->gpc2clk_target_mhz = target_mhz * 2ULL;
break; break;
@@ -1659,12 +1657,10 @@ int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
switch (api_domain) { switch (api_domain) {
case NVGPU_GPU_CLK_DOMAIN_MCLK: case NVGPU_GPU_CLK_DOMAIN_MCLK:
case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
*freq_mhz = target->mclk; *freq_mhz = target->mclk;
break; break;
case NVGPU_GPU_CLK_DOMAIN_GPCCLK: case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
*freq_mhz = target->gpc2clk / 2ULL; *freq_mhz = target->gpc2clk / 2ULL;
break; break;
@@ -1690,12 +1686,10 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
switch (api_domain) { switch (api_domain) {
case NVGPU_GPU_CLK_DOMAIN_MCLK: case NVGPU_GPU_CLK_DOMAIN_MCLK:
case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
*freq_mhz = actual->mclk; *freq_mhz = actual->mclk;
break; break;
case NVGPU_GPU_CLK_DOMAIN_GPCCLK: case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
*freq_mhz = actual->gpc2clk / 2ULL; *freq_mhz = actual->gpc2clk / 2ULL;
break; break;
@@ -1712,12 +1706,10 @@ int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
{ {
switch(api_domain) { switch(api_domain) {
case NVGPU_GPU_CLK_DOMAIN_MCLK: case NVGPU_GPU_CLK_DOMAIN_MCLK:
case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
*freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_MCLK); *freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_MCLK);
return 0; return 0;
case NVGPU_GPU_CLK_DOMAIN_GPCCLK: case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
*freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPC2CLK) / 2; *freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPC2CLK) / 2;
return 0; return 0;
@@ -1733,13 +1725,11 @@ int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
switch(api_domain) { switch(api_domain) {
case NVGPU_GPU_CLK_DOMAIN_MCLK: case NVGPU_GPU_CLK_DOMAIN_MCLK:
case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
ret = g->ops.clk_arb.get_arbiter_clk_range(g, ret = g->ops.clk_arb.get_arbiter_clk_range(g,
CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz);
return ret; return ret;
case NVGPU_GPU_CLK_DOMAIN_GPCCLK: case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
ret = g->ops.clk_arb.get_arbiter_clk_range(g, ret = g->ops.clk_arb.get_arbiter_clk_range(g,
CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz);
if (!ret) { if (!ret) {
@@ -1759,10 +1749,10 @@ u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
u32 api_domains = 0; u32 api_domains = 0;
if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK)
api_domains |= NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS; api_domains |= BIT(NVGPU_GPU_CLK_DOMAIN_GPCCLK);
if (clk_domains & CTRL_CLK_DOMAIN_MCLK) if (clk_domains & CTRL_CLK_DOMAIN_MCLK)
api_domains |= NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS; api_domains |= BIT(NVGPU_GPU_CLK_DOMAIN_MCLK);
return api_domains; return api_domains;
} }
@@ -1773,11 +1763,9 @@ bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain)
switch(api_domain) { switch(api_domain) {
case NVGPU_GPU_CLK_DOMAIN_MCLK: case NVGPU_GPU_CLK_DOMAIN_MCLK:
case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0); return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0);
case NVGPU_GPU_CLK_DOMAIN_GPCCLK: case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0); return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0);
default: default:
@@ -1793,7 +1781,6 @@ int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
switch (api_domain) { switch (api_domain) {
case NVGPU_GPU_CLK_DOMAIN_GPCCLK: case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS:
err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK, err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK,
max_points, fpoints); max_points, fpoints);
if (err || !fpoints) if (err || !fpoints)
@@ -1802,7 +1789,6 @@ int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
fpoints[i] /= 2; fpoints[i] /= 2;
return 0; return 0;
case NVGPU_GPU_CLK_DOMAIN_MCLK: case NVGPU_GPU_CLK_DOMAIN_MCLK:
case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS:
return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK, return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK,
max_points, fpoints); max_points, fpoints);
default: default:

10
drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c
View File

@@ -987,10 +987,7 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g,
return -EFAULT; return -EFAULT;
} else { } else {
bit = ffs(clk_domains) - 1; bit = ffs(clk_domains) - 1;
if (bit <= NVGPU_GPU_CLK_DOMAIN_GPCCLK) clk_range.clk_domain = bit;
clk_range.clk_domain = bit;
else
clk_range.clk_domain = BIT(bit);
clk_domains &= ~BIT(bit); clk_domains &= ~BIT(bit);
} }
@@ -1139,10 +1136,7 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g,
return -EFAULT; return -EFAULT;
} else { } else {
bit = ffs(clk_domains) - 1; bit = ffs(clk_domains) - 1;
if (bit <= NVGPU_GPU_CLK_DOMAIN_GPCCLK) clk_info.clk_domain = bit;
clk_info.clk_domain = bit;
else
clk_info.clk_domain = BIT(bit);
clk_domains &= ~BIT(bit); clk_domains &= ~BIT(bit);
clk_info.clk_type = args->clk_type; clk_info.clk_type = args->clk_type;
} }

2
include/uapi/linux/nvgpu.h
View File

@@ -541,10 +541,8 @@ struct nvgpu_gpu_alloc_vidmem_args {
/* Memory clock */ /* Memory clock */
#define NVGPU_GPU_CLK_DOMAIN_MCLK (0) #define NVGPU_GPU_CLK_DOMAIN_MCLK (0)
#define NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS (0x00000010)
/* Main graphics core clock */ /* Main graphics core clock */
#define NVGPU_GPU_CLK_DOMAIN_GPCCLK (1) #define NVGPU_GPU_CLK_DOMAIN_GPCCLK (1)
#define NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS (0x10000000)
struct nvgpu_gpu_clk_range { struct nvgpu_gpu_clk_range {