From 0984189be41af44bafc066125f8d61f347bd7986 Mon Sep 17 00:00:00 2001 From: rmylavarapu Date: Thu, 21 Nov 2019 11:05:42 +0530 Subject: [PATCH] gpu: nvgpu: Remove clk_freq_domain unit Removed clk_freq_domain unit as it is no longer support by auto profile. NVGPU-4392 Change-Id: Iebad4bec8a98447e58fea5735124d25a8664ce5d Signed-off-by: rmylavarapu Reviewed-on: https://git-master.nvidia.com/r/2243990 Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- arch/nvgpu-common.yaml | 6 - drivers/gpu/nvgpu/Makefile | 1 - drivers/gpu/nvgpu/Makefile.sources | 1 - .../nvgpu/common/pmu/clk/clk_freq_domain.c | 264 ------------------ drivers/gpu/nvgpu/common/pmu/pmu_pstate.c | 23 -- .../pmu/super_surface/super_surface_priv.h | 2 - drivers/gpu/nvgpu/hal/init/hal_tu104.c | 1 - drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 - drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h | 2 - .../include/nvgpu/pmu/clk/clk_freq_domain.h | 49 ---- .../gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h | 17 -- .../nvgpu/include/nvgpu/pmu/pmuif/ctrlclk.h | 11 - 12 files changed, 378 deletions(-) delete mode 100644 drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c delete mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index cb8b9d7d2..daabf0a1f 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -797,12 +797,6 @@ pmu: sources: [ common/pmu/clk/clk_vin.c, common/pmu/clk/clk_vin.h, include/nvgpu/pmu/clk/clk_vin.h ] - - freq_domain: - safe: yes - gpu: dgpu - sources: [ common/pmu/clk/clk_freq_domain.c, - include/nvgpu/pmu/clk/clk_freq_domain.h ] ipc: safe: yes owner: Sagar K diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 86ccf775d..11758411d 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -173,7 +173,6 @@ nvgpu-y += \ common/pmu/clk/clk_vin.o \ common/pmu/clk/clk_fll.o \ common/pmu/clk/clk_domain.o \ - common/pmu/clk/clk_freq_domain.o \ common/pmu/clk/clk_prog.o \ common/pmu/clk/clk_vf_point.o \ common/pmu/clk/clk.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index a352ceff1..091845223 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -435,7 +435,6 @@ srcs += \ common/pmu/boardobj/boardobjgrp_e32.c \ common/pmu/clk/clk.c \ common/pmu/clk/clk_domain.c \ - common/pmu/clk/clk_freq_domain.c \ common/pmu/clk/clk_fll.c \ common/pmu/clk/clk_prog.c \ common/pmu/clk/clk_vf_point.c \ diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c deleted file mode 100644 index 14cbe19fd..000000000 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_domain.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct domain_type { - u8 type; - u32 clk_domain; -}; - -static struct domain_type clk_freq_domain_type[] = { - { - CTRL_CLK_FREQ_DOMAIN_SCHEMA_MULTI_FLL, - CTRL_CLK_DOMAIN_GPCCLK, - }, - { - CTRL_CLK_FREQ_DOMAIN_SCHEMA_SINGLE_FLL, - CTRL_CLK_DOMAIN_XBARCLK, - }, - { - CTRL_CLK_FREQ_DOMAIN_SCHEMA_SINGLE_FLL, - CTRL_CLK_DOMAIN_SYSCLK, - }, - { - CTRL_CLK_FREQ_DOMAIN_SCHEMA_SINGLE_FLL, - CTRL_CLK_DOMAIN_NVDCLK, - }, - { - CTRL_CLK_FREQ_DOMAIN_SCHEMA_SINGLE_FLL, - CTRL_CLK_DOMAIN_HOSTCLK, - }, -}; - -static int clk_freq_domain_grp_pmudatainit(struct gk20a *g, - struct boardobjgrp *pboardobjgrp, - struct nv_pmu_boardobjgrp_super *pboardobjgrppmu) -{ - struct nv_pmu_clk_clk_freq_domain_boardobjgrp_set_header *pset = - (struct nv_pmu_clk_clk_freq_domain_boardobjgrp_set_header *) - pboardobjgrppmu; - struct nvgpu_clk_freq_domain_grp *pfreq_domain_grp = - (struct nvgpu_clk_freq_domain_grp *)pboardobjgrp; - int status = 0; - - status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); - if (status != 0) { - nvgpu_err(g, - "error updating pmu boardobjgrp for " - "clk freq domain 0x%x", status); - goto exit; - } - - pset->init_flags = pfreq_domain_grp->init_flags; - -exit: - return status; -} - -static int clk_freq_domain_grp_pmudata_instget(struct gk20a *g, - struct nv_pmu_boardobjgrp *pmuboardobjgrp, - struct nv_pmu_boardobj **ppboardobjpmudata, - u8 idx) -{ - struct nv_pmu_clk_clk_freq_domain_boardobj_grp_set *pgrp_set = - (struct nv_pmu_clk_clk_freq_domain_boardobj_grp_set *) - pmuboardobjgrp; - - nvgpu_log_fn(g, " "); - - /*check whether pmuboardobjgrp has a valid boardobj in index*/ - if (((u32)BIT(idx) & - pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { - nvgpu_err(g, "bit(idx)==0"); - return -EINVAL; - } - - *ppboardobjpmudata = (struct nv_pmu_boardobj *) - &pgrp_set->objects[idx].data.super; - - return 0; -} - - -static int clk_freq_domain_pmudatainit(struct gk20a *g, - struct boardobj *board_obj_ptr, - struct nv_pmu_boardobj *ppmudata) -{ - struct nv_pmu_clk_clk_freq_domain_boardobj_set *pset = NULL; - struct nvgpu_clk_freq_domain *freq_domain = NULL; - int status = 0; - - nvgpu_log_fn(g, " "); - - status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata); - if(status != 0) { - nvgpu_err(g, "Failed pmudatainit freq_domain"); - goto exit; - } - - freq_domain = (struct nvgpu_clk_freq_domain *)(void*)board_obj_ptr; - pset = (struct nv_pmu_clk_clk_freq_domain_boardobj_set *) - (void*)ppmudata; - pset->clk_domain = freq_domain->clk_domain; - -exit: - return status; -} - -int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g) -{ - struct boardobjgrp *pboardobjgrp = NULL; - struct boardobj *pboardobj = NULL; - struct nvgpu_clk_freq_domain *pfreq_domain = NULL; - struct nvgpu_clk_freq_domain_grp *pfreq_domain_grp = NULL; - size_t tmp_num_of_domains = sizeof(clk_freq_domain_type) / - sizeof(struct domain_type); - u8 num_of_domains; - int status = 0; - u8 idx = 0; - - union { - struct boardobj super; - struct nvgpu_clk_freq_domain freq_domain; - }freq_domain_data; - - nvgpu_assert(tmp_num_of_domains <= U8_MAX); - num_of_domains = (u8)tmp_num_of_domains; - - pboardobjgrp = &g->pmu->clk_pmu->freq_domain_grp_objs->super.super; - pfreq_domain_grp = g->pmu->clk_pmu->freq_domain_grp_objs; - - status = nvgpu_boardobjgrp_construct_e32(g, - &g->pmu->clk_pmu->freq_domain_grp_objs->super); - if (status != 0) { - nvgpu_err(g, - "error creating boardobjgrp for clk freq domain, " - "status - 0x%x", status); - goto exit; - } - - pfreq_domain_grp->super.super.pmudatainit = - clk_freq_domain_grp_pmudatainit; - pfreq_domain_grp->super.super.pmudatainstget = - clk_freq_domain_grp_pmudata_instget; - - /* No need to report */ - pfreq_domain_grp->init_flags = 0U; - - BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_FREQ_DOMAIN); - - status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, - clk, CLK, clk_freq_domain, CLK_FREQ_DOMAIN); - if (status != 0) { - nvgpu_err(g, - "error constructing PMU_BOARDOBJ_CMD_GRP_SET " - "interface - 0x%x", status); - goto exit; - } - - for (idx = 0; idx < num_of_domains; idx++) { - (void) memset(&freq_domain_data, 0, sizeof(freq_domain_data)); - - freq_domain_data.super.type = clk_freq_domain_type[idx].type; - freq_domain_data.freq_domain.clk_domain = - clk_freq_domain_type[idx].clk_domain; - - pboardobj = NULL; - status = nvgpu_boardobj_construct_super(g,&pboardobj, - sizeof(struct nvgpu_clk_freq_domain), - (void*)&freq_domain_data); - if(status != 0) { - nvgpu_err(g, "Failed to construct " - "nvgpu_clk_freq_domain Board obj"); - goto exit; - } - - pfreq_domain = (struct nvgpu_clk_freq_domain*)(void*) pboardobj; - pfreq_domain->super.pmudatainit = clk_freq_domain_pmudatainit; - pfreq_domain->clk_domain = - freq_domain_data.freq_domain.clk_domain; - - status = boardobjgrp_objinsert(&pfreq_domain_grp->super.super, - &pfreq_domain->super, idx); - if (status != 0) { - nvgpu_err(g, - "unable to insert clock freq domain " - "boardobj for %d", idx); - goto exit; - } - } - -exit: - return status; -} - -int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g) -{ - int status = 0; - struct boardobjgrp *pboardobjgrp = NULL; - - nvgpu_log_fn(g, " "); - - pboardobjgrp = &g->pmu->clk_pmu->freq_domain_grp_objs->super.super; - - if (!pboardobjgrp->bconstructed) { - return -EINVAL; - } - - status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); - - return status; - -} - -int nvgpu_clk_freq_domain_init_pmupstate(struct gk20a *g) -{ - /* If already allocated, do not re-allocate */ - if (g->pmu->clk_pmu->freq_domain_grp_objs != NULL) { - return 0; - } - - g->pmu->clk_pmu->freq_domain_grp_objs = nvgpu_kzalloc(g, - sizeof(*g->pmu->clk_pmu->freq_domain_grp_objs)); - if (g->pmu->clk_pmu->freq_domain_grp_objs == NULL) { - return -ENOMEM; - } - - return 0; -} - -void nvgpu_clk_freq_domain_free_pmupstate(struct gk20a *g) -{ - nvgpu_kfree(g, g->pmu->clk_pmu->freq_domain_grp_objs); - g->pmu->clk_pmu->freq_domain_grp_objs = NULL; -} diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c index e11615fb1..7fbd51237 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include @@ -56,7 +55,6 @@ void nvgpu_pmu_pstate_deinit(struct gk20a *g) nvgpu_clk_domain_free_pmupstate(g); nvgpu_clk_prog_free_pmupstate(g); nvgpu_clk_vf_point_free_pmupstate(g); - nvgpu_clk_freq_domain_free_pmupstate(g); nvgpu_clk_fll_free_pmupstate(g); nvgpu_clk_vin_free_pmupstate(g); nvgpu_clk_free_pmupstate(g); @@ -96,12 +94,6 @@ static int pmu_pstate_clk_init(struct gk20a *g) return err; } - err = nvgpu_clk_freq_domain_init_pmupstate(g); - if (err != 0) { - nvgpu_clk_freq_domain_free_pmupstate(g); - return err; - } - err = nvgpu_clk_vin_init_pmupstate(g); if (err != 0) { nvgpu_clk_vin_free_pmupstate(g); @@ -209,14 +201,6 @@ static int pmu_pstate_clk_sw_setup(struct gk20a *g) return err; } - if (g->ops.clk.support_clk_freq_domain) { - err = nvgpu_clk_freq_domain_sw_setup(g); - if (err != 0) { - nvgpu_clk_freq_domain_free_pmupstate(g); - return err; - } - } - return 0; } @@ -370,13 +354,6 @@ static int pmu_pstate_clk_pmu_setup(struct gk20a *g) return err; } - if (g->ops.clk.support_clk_freq_domain) { - err = nvgpu_clk_freq_domain_pmu_setup(g); - if (err != 0) { - return err; - } - } - err = nvgpu_clk_fll_pmu_setup(g); if (err != 0) { return err; diff --git a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h index fe943c021..2ff363c6c 100644 --- a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h +++ b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h @@ -139,8 +139,6 @@ struct nv_pmu_super_surface { clk_fll_device_grp_get_status; struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status; - struct nv_pmu_clk_clk_freq_domain_boardobj_grp_set - clk_freq_domain_grp_set; } clk; struct { struct nv_pmu_perf_vfe_equ_boardobj_grp_set_pack diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index c93db7193..a8aa52f91 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -1653,7 +1653,6 @@ int tu104_init_hal(struct gk20a *g) /* for now */ gops->clk.support_pmgr_domain = false; gops->clk.support_lpwr_pg = false; - gops->clk.support_clk_freq_domain = false; gops->pmu_perf.support_changeseq = true; gops->pmu_perf.support_vfe = true; gops->clk.support_vf_point = true; diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 66851bbfa..967f40b37 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -365,7 +365,6 @@ struct gpu_ops { bool support_pmgr_domain; bool support_lpwr_pg; int (*perf_pmu_vfe_load)(struct gk20a *g); - bool support_clk_freq_domain; bool support_vf_point; u8 lut_num_entries; bool (*clk_mon_check_master_fault_status)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h index 1c5fb7b4f..110f55357 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h @@ -33,7 +33,6 @@ struct nvgpu_clk_domains; struct nvgpu_clk_progs; struct nvgpu_clk_vf_points; struct nvgpu_clk_mclk_state; -struct nvgpu_clk_freq_domain_grp; struct nvgpu_clk_slave_freq; struct ctrl_perf_change_seq_change_input; @@ -69,7 +68,6 @@ struct nvgpu_clk_pmupstate { struct nvgpu_clk_domains *clk_domainobjs; struct nvgpu_clk_progs *clk_progobjs; struct nvgpu_clk_vf_points *clk_vf_pointobjs; - struct nvgpu_clk_freq_domain_grp *freq_domain_grp_objs; /* clk_domain unit functions */ int (*get_fll)(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk); diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h deleted file mode 100644 index 32e3ff55c..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * general clock structures & definitions - * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_PMU_CLK_FREQ_DOMAIN_H -#define NVGPU_PMU_CLK_FREQ_DOMAIN_H - -#include -#include - -struct gk20a; -struct boardobjgrp_e32; - -struct nvgpu_clk_freq_domain_grp { - struct boardobjgrp_e32 super; - u32 init_flags; -}; - -struct nvgpu_clk_freq_domain { - struct boardobj super; - u32 clk_domain; -}; - -int nvgpu_clk_freq_domain_init_pmupstate(struct gk20a *g); -void nvgpu_clk_freq_domain_free_pmupstate(struct gk20a *g); -int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g); -int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g); - -#endif /* NVGPU_PMU_CLK_FREQ_DOMAIN_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h index cb08617db..5983423f6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h @@ -612,23 +612,6 @@ union nv_pmu_clk_clk_fll_device_boardobj_get_status_union { NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device); -struct nv_pmu_clk_clk_freq_domain_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - u32 init_flags; -}; - -struct nv_pmu_clk_clk_freq_domain_boardobj_set { - struct nv_pmu_boardobj super; - u32 clk_domain; -}; - -union nv_pmu_clk_clk_freq_domain_boardobj_set_union { - struct nv_pmu_boardobj super; - struct nv_pmu_clk_clk_freq_domain_boardobj_set domain; -}; -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_domain); - - struct nv_pmu_rpc_clk_domain_35_prog_freq_to_volt { /*[IN/OUT] Must be first field in RPC structure */ struct nv_pmu_rpc_header hdr; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclk.h index c32ba31f1..8eb190866 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclk.h @@ -317,15 +317,4 @@ struct clk_domains_mon_status_params { #define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \ (((pvfpair)->voltage_uv) = (_voltageuv)) -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_BIF 0x01U -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_OSM 0x02U -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_MCLK 0x03U -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_PLL_LDIV 0x04U -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_PLL_XCLK 0x05U -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_SINGLE_FLL 0x06U -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_MULTI_FLL 0x07U -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_SWDIV 0x08U -#define CTRL_CLK_FREQ_DOMAIN_SCHEMA_STUB 0x09U - - #endif /* NVGPU_PMUIF_CTRLCLK_H */