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git://nv-tegra.nvidia.com/linux-nvgpu.git
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gpu: nvgpu: move gv11b code under config flag
Move gv11b specific code under CONFIG_NVGPU_GV11B_SUPPORT so that gv11b
support can be removed for qnx later as it is no longer POR for qnx on
dev-main.
Jira NVGPU-8189
Bug 3642168
Change-Id: Idc17cfa22199f2b69a1bab0849cd2bd2e0fb6288
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2693828
(cherry picked from commit ba22f6263b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2725975
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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@@ -367,7 +367,6 @@ nvgpu-y += \
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hal/gr/gr/gr_gv100.o \
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hal/gr/gr/gr_gv100.o \
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hal/gr/gr/gr_gv11b.o \
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hal/gr/gr/gr_gv11b.o \
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hal/gr/gr/gr_tu104.o \
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hal/gr/gr/gr_tu104.o \
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hal/init/hal_gv11b.o \
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hal/init/hal_gv11b_litter.o \
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hal/init/hal_gv11b_litter.o \
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hal/init/hal_init.o \
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hal/init/hal_init.o \
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hal/perf/perf_gv11b.o \
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hal/perf/perf_gv11b.o \
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@@ -415,6 +414,11 @@ nvgpu-y += \
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hal/cic/mon/init_ga10b_fusa.o \
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hal/cic/mon/init_ga10b_fusa.o \
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hal/cic/mon/lut_ga10b_fusa.o
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hal/cic/mon/lut_ga10b_fusa.o
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ifeq ($(CONFIG_NVGPU_SUPPORT_GV11B),y)
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nvgpu-$(CONFIG_NVGPU_SUPPORT_GV11B) += \
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hal/init/hal_gv11b.o
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endif
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ifeq ($(CONFIG_NVGPU_INTR_DEBUG),y)
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ifeq ($(CONFIG_NVGPU_INTR_DEBUG),y)
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nvgpu-$(CONFIG_NVGPU_INTR_DEBUG) += \
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nvgpu-$(CONFIG_NVGPU_INTR_DEBUG) += \
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common/cic/mon/mon_ce.o \
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common/cic/mon/mon_ce.o \
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@@ -41,6 +41,9 @@ CONFIG_NVGPU_COMPRESSION := y
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# Enable MIG Support
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# Enable MIG Support
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CONFIG_NVGPU_MIG := y
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CONFIG_NVGPU_MIG := y
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# Enable gv11b support
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CONFIG_NVGPU_SUPPORT_GV11B := y
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# Enable support for extraction of comptags for CDE.
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# Enable support for extraction of comptags for CDE.
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ifeq ($(CONFIG_NVGPU_COMPRESSION),y)
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ifeq ($(CONFIG_NVGPU_COMPRESSION),y)
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CONFIG_NVGPU_SUPPORT_CDE := y
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CONFIG_NVGPU_SUPPORT_CDE := y
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@@ -213,6 +216,9 @@ endif
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ifeq ($(CONFIG_NVGPU_COMPRESSION),y)
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ifeq ($(CONFIG_NVGPU_COMPRESSION),y)
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ccflags-y += -DCONFIG_NVGPU_COMPRESSION
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ccflags-y += -DCONFIG_NVGPU_COMPRESSION
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endif
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endif
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ifeq ($(CONFIG_NVGPU_SUPPORT_GV11B),y)
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ccflags-y += -DCONFIG_NVGPU_SUPPORT_GV11B
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endif
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ifeq ($(CONFIG_NVGPU_REMAP),y)
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ifeq ($(CONFIG_NVGPU_REMAP),y)
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ccflags-y += -DCONFIG_NVGPU_REMAP
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ccflags-y += -DCONFIG_NVGPU_REMAP
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endif
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endif
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@@ -78,6 +78,9 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SYNCFD_NONE
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CONFIG_NVGPU_GRAPHICS := 1
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CONFIG_NVGPU_GRAPHICS := 1
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NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_GRAPHICS
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NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_GRAPHICS
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CONFIG_NVGPU_SUPPORT_GV11B := 1
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NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SUPPORT_GV11B
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# Error reporting needs to be supported in qnx-safety, qnx-standard, linux.
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# Error reporting needs to be supported in qnx-safety, qnx-standard, linux.
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# In qnx-standard, nvgpu makefile is used for RM SERVER. Since iGPU is in
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# In qnx-standard, nvgpu makefile is used for RM SERVER. Since iGPU is in
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# pass through mode in all three platforms, EPL libraries should not be
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# pass through mode in all three platforms, EPL libraries should not be
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@@ -165,7 +165,6 @@ srcs += common/device.c \
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common/cic/mon/mon_report_err.c \
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common/cic/mon/mon_report_err.c \
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common/cic/rm/rm_init.c \
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common/cic/rm/rm_init.c \
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common/cic/rm/rm_intr.c \
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common/cic/rm/rm_intr.c \
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hal/init/hal_gv11b.c \
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hal/init/hal_gv11b_litter.c \
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hal/init/hal_gv11b_litter.c \
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hal/init/hal_init.c \
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hal/init/hal_init.c \
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hal/power_features/cg/gv11b_gating_reglist.c \
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hal/power_features/cg/gv11b_gating_reglist.c \
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@@ -299,6 +298,10 @@ ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
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srcs += hal/cbc/cbc_tu104.c
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srcs += hal/cbc/cbc_tu104.c
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endif
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endif
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ifeq ($(CONFIG_NVGPU_SUPPORT_GV11B),1)
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srcs += hal/init/hal_gv11b.c
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endif
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# Source files below are not guaranteed to be functionaly safe (FuSa) and are
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# Source files below are not guaranteed to be functionaly safe (FuSa) and are
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# only included in the normal build.
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# only included in the normal build.
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ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
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ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
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@@ -1,7 +1,7 @@
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/*
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/*
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* NVIDIA GPU HAL interface.
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* NVIDIA GPU HAL interface.
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*
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*
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* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* copy of this software and associated documentation files (the "Software"),
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@@ -68,11 +68,13 @@ int nvgpu_init_hal(struct gk20a *g)
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err = -ENODEV;
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err = -ENODEV;
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}
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}
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break;
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break;
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#ifdef CONFIG_NVGPU_SUPPORT_GV11B
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case NVGPU_GPUID_GV11B:
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case NVGPU_GPUID_GV11B:
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if (gv11b_init_hal(g) != 0) {
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if (gv11b_init_hal(g) != 0) {
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err = -ENODEV;
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err = -ENODEV;
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}
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}
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break;
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break;
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#endif
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#if defined(CONFIG_NVGPU_DGPU) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
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#if defined(CONFIG_NVGPU_DGPU) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
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case NVGPU_GPUID_TU104:
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case NVGPU_GPUID_TU104:
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@@ -121,6 +123,7 @@ int nvgpu_detect_chip(struct gk20a *g)
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return -ENODEV;
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return -ENODEV;
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}
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}
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#ifdef CONFIG_NVGPU_SUPPORT_GV11B
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if (nvgpu_safe_add_u32(p->gpu_arch, p->gpu_impl) ==
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if (nvgpu_safe_add_u32(p->gpu_arch, p->gpu_impl) ==
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(u32)NVGPU_GPUID_GV11B) {
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(u32)NVGPU_GPUID_GV11B) {
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/* overwrite gpu revison for A02 */
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/* overwrite gpu revison for A02 */
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@@ -128,6 +131,7 @@ int nvgpu_detect_chip(struct gk20a *g)
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p->gpu_rev = 0xa2;
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p->gpu_rev = 0xa2;
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}
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}
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}
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}
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#endif
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nvgpu_log_info(g, "arch: %x, impl: %x, rev: %x\n",
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nvgpu_log_info(g, "arch: %x, impl: %x, rev: %x\n",
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g->params.gpu_arch,
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g->params.gpu_arch,
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g->params.gpu_impl,
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g->params.gpu_impl,
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