diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 2b410ab03..ce731ea72 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -27,8 +27,6 @@ obj-$(CONFIG_GK20A) := nvgpu.o # is in progress. nvgpu-y += \ - common/priv_ring/priv_ring_gm20b.o \ - common/priv_ring/priv_ring_gp10b.o \ common/ptimer/ptimer.o \ common/ptimer/ptimer_gk20a.o \ common/fb/fb_gm20b.o \ @@ -163,7 +161,9 @@ nvgpu-y += \ hal/bus/bus_gm20b.o \ hal/bus/bus_gp10b.o \ hal/bus/bus_gv100.o \ - hal/bus/bus_tu104.o + hal/bus/bus_tu104.o \ + hal/priv_ring/priv_ring_gm20b.o \ + hal/priv_ring/priv_ring_gp10b.o # Linux specific parts of nvgpu. nvgpu-y += \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index ba04d661b..5e13206c0 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -77,8 +77,6 @@ srcs += common/sim.c \ common/mm/mm.c \ common/mm/dma.c \ common/mm/vidmem.c \ - common/priv_ring/priv_ring_gm20b.c \ - common/priv_ring/priv_ring_gp10b.c \ common/fb/fb_gm20b.c \ common/fb/fb_gp10b.c \ common/fb/fb_gp106.c \ @@ -339,7 +337,9 @@ srcs += common/sim.c \ hal/bus/bus_gm20b.c \ hal/bus/bus_gp10b.c \ hal/bus/bus_gv100.c \ - hal/bus/bus_tu104.c + hal/bus/bus_tu104.c \ + hal/priv_ring/priv_ring_gm20b.c \ + hal/priv_ring/priv_ring_gp10b.c ifeq ($(NVGPU_DEBUGGER),1) srcs += common/debugger.c diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index 6d66c89b9..a1ef6238b 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -23,8 +23,6 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gm20b.h" -#include "common/priv_ring/priv_ring_gm20b.h" -#include "common/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/gp10b_gating_reglist.h" #include "common/fb/fb_gm20b.h" #include "common/fb/fb_gp10b.h" diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index 2905dc8d4..2c220258f 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -22,8 +22,7 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gm20b.h" -#include "common/priv_ring/priv_ring_gm20b.h" -#include "common/priv_ring/priv_ring_gp10b.h" + #include "common/clock_gating/gv11b_gating_reglist.h" #include "common/fb/fb_gm20b.h" #include "common/fb/fb_gp10b.h" diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index a7d95e0b2..e4f91622b 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -39,9 +39,9 @@ #include "hal/bus/bus_gm20b.h" #include "hal/bus/bus_gk20a.h" +#include "hal/priv_ring/priv_ring_gm20b.h" #include "common/clock_gating/gm20b_gating_reglist.h" -#include "common/priv_ring/priv_ring_gm20b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" #include "common/netlist/netlist_gm20b.h" diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 98090b565..fb8aaec25 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -42,11 +42,11 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gm20b.h" #include "hal/bus/bus_gp10b.h" +#include "hal/priv_ring/priv_ring_gm20b.h" +#include "hal/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/gp10b_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" -#include "common/priv_ring/priv_ring_gm20b.h" -#include "common/priv_ring/priv_ring_gp10b.h" #include "common/fb/fb_gm20b.h" #include "common/fb/fb_gp10b.h" #include "common/netlist/netlist_gp10b.h" diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 645eb2c0d..f8c6e0004 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -25,9 +25,9 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gp10b.h" #include "hal/bus/bus_gv100.h" +#include "hal/priv_ring/priv_ring_gm20b.h" +#include "hal/priv_ring/priv_ring_gp10b.h" -#include "common/priv_ring/priv_ring_gm20b.h" -#include "common/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/gv100_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9b142c43f..1130a7fb2 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -28,9 +28,9 @@ #include "hal/bus/bus_gk20a.h" #include "hal/bus/bus_gp10b.h" #include "hal/bus/bus_gm20b.h" +#include "hal/priv_ring/priv_ring_gm20b.h" +#include "hal/priv_ring/priv_ring_gp10b.h" -#include "common/priv_ring/priv_ring_gm20b.h" -#include "common/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/gv11b_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h" diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.c similarity index 62% rename from drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c rename to drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.c index 8fb5485a2..7938f6b65 100644 --- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.c @@ -1,5 +1,7 @@ /* - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * GM20B priv ring + * + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -36,72 +38,83 @@ void gm20b_priv_ring_enable(struct gk20a *g) { if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + nvgpu_log_info(g, "priv ring is already enabled"); return; } - nvgpu_log(g, gpu_dbg_info, "enabling priv ring"); + nvgpu_log_info(g, "enabling priv ring"); if (g->ops.clock_gating.slcg_priring_load_gating_prod != NULL) { g->ops.clock_gating.slcg_priring_load_gating_prod(g, g->slcg_enabled); } - gk20a_writel(g,pri_ringmaster_command_r(), - 0x4); + nvgpu_writel(g,pri_ringmaster_command_r(), 0x4); - gk20a_writel(g, pri_ringstation_sys_decode_config_r(), - 0x2); - (void) gk20a_readl(g, pri_ringstation_sys_decode_config_r()); + nvgpu_writel(g, pri_ringstation_sys_decode_config_r(), 0x2); + + (void) nvgpu_readl(g, pri_ringstation_sys_decode_config_r()); } void gm20b_priv_ring_isr(struct gk20a *g) { u32 status0, status1; u32 cmd; - s32 retry = 100; + s32 retry; u32 gpc; - u32 gpc_priv_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE); + u32 gpc_priv_stride; + u32 gpc_offset; if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + nvgpu_err(g, "unhandled priv ring intr"); return; } - status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); - status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); + status0 = nvgpu_readl(g, pri_ringmaster_intr_status0_r()); + status1 = nvgpu_readl(g, pri_ringmaster_intr_status1_r()); nvgpu_log(g, gpu_dbg_intr, "ringmaster intr status0: 0x%08x," "status1: 0x%08x", status0, status1); if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0U) { - nvgpu_log(g, gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", - gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), - gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), - gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), - gk20a_readl(g, pri_ringstation_sys_priv_error_code_r())); + nvgpu_log(g, gpu_dbg_intr, "SYS write error. ADR %08x " + "WRDAT %08x INFO %08x, CODE %08x", + nvgpu_readl(g, pri_ringstation_sys_priv_error_adr_r()), + nvgpu_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), + nvgpu_readl(g, pri_ringstation_sys_priv_error_info_r()), + nvgpu_readl(g, pri_ringstation_sys_priv_error_code_r())); } + gpc_priv_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE); + for (gpc = 0; gpc < g->ops.priv_ring.get_gpc_count(g); gpc++) { - if ((status1 & BIT32(gpc)) != 0U) { - nvgpu_log(g, gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_priv_stride)); + if ((status1 & BIT32(gpc)) == 0U) { + continue; } + gpc_offset = gpc * gpc_priv_stride; + nvgpu_log(g, gpu_dbg_intr, "GPC%u write error. ADR %08x " + "WRDAT %08x INFO %08x, CODE %08x", gpc, + nvgpu_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc_offset), + nvgpu_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc_offset), + nvgpu_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc_offset), + nvgpu_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc_offset)); } /* clear interrupt */ - cmd = gk20a_readl(g, pri_ringmaster_command_r()); + cmd = nvgpu_readl(g, pri_ringmaster_command_r()); cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), pri_ringmaster_command_cmd_ack_interrupt_f()); - gk20a_writel(g, pri_ringmaster_command_r(), cmd); + nvgpu_writel(g, pri_ringmaster_command_r(), cmd); + /* poll for clear interrupt done */ + retry = GM20B_PRIV_RING_POLL_CLEAR_INTR_RETRIES; + cmd = pri_ringmaster_command_cmd_v( - gk20a_readl(g, pri_ringmaster_command_r())); + nvgpu_readl(g, pri_ringmaster_command_r())); while ((cmd != pri_ringmaster_command_cmd_no_cmd_v()) && (retry != 0)) { - nvgpu_udelay(20); + nvgpu_udelay(GM20B_PRIV_RING_POLL_CLEAR_INTR_UDELAY); retry--; cmd = pri_ringmaster_command_cmd_v( - gk20a_readl(g, pri_ringmaster_command_r())); + nvgpu_readl(g, pri_ringmaster_command_r())); } if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v()) { nvgpu_warn(g, "priv ringmaster intr ack too many retries"); @@ -120,7 +133,7 @@ void gm20b_priv_set_timeout_settings(struct gk20a *g) u32 gm20b_priv_ring_enum_ltc(struct gk20a *g) { - return gk20a_readl(g, pri_ringmaster_enum_ltc_r()); + return nvgpu_readl(g, pri_ringmaster_enum_ltc_r()); } u32 gm20b_priv_ring_get_gpc_count(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.h similarity index 89% rename from drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h rename to drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.h index 6bd0a2f92..e79a24b02 100644 --- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -24,6 +24,9 @@ struct gk20a; +#define GM20B_PRIV_RING_POLL_CLEAR_INTR_RETRIES 100 +#define GM20B_PRIV_RING_POLL_CLEAR_INTR_UDELAY 20 + void gm20b_priv_ring_isr(struct gk20a *g); void gm20b_priv_ring_enable(struct gk20a *g); void gm20b_priv_set_timeout_settings(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.c similarity index 72% rename from drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c rename to drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.c index 1cf8df587..282b59aa1 100644 --- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B priv ring * - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -106,9 +106,9 @@ void gp10b_priv_ring_isr(struct gk20a *g) { u32 status0, status1; u32 cmd; - s32 retry = 100; + s32 retry; u32 gpc; - u32 gpc_stride, offset; + u32 gpc_stride, gpc_offset; u32 error_info; u32 error_code; @@ -117,11 +117,11 @@ void gp10b_priv_ring_isr(struct gk20a *g) return; } - status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); - status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); + status0 = nvgpu_readl(g, pri_ringmaster_intr_status0_r()); + status1 = nvgpu_readl(g, pri_ringmaster_intr_status1_r()); - nvgpu_err(g, "ringmaster intr status0: 0x%08x," - "status1: 0x%08x", status0, status1); + nvgpu_err(g, "ringmaster intr status0: 0x%08x, status1: 0x%08x", + status0, status1); if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0U) { nvgpu_err(g, @@ -138,14 +138,14 @@ void gp10b_priv_ring_isr(struct gk20a *g) if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0U) { error_info = - gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()); + nvgpu_readl(g, pri_ringstation_sys_priv_error_info_r()); error_code = - gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()); + nvgpu_readl(g, pri_ringstation_sys_priv_error_code_r()); nvgpu_err(g, "SYS write error. ADR 0x%08x WRDAT 0x%08x " "INFO 0x%08x (subid 0x%08x priv level %d), " "CODE 0x%08x", - gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), - gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), + nvgpu_readl(g, pri_ringstation_sys_priv_error_adr_r()), + nvgpu_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), error_info, pri_ringstation_sys_priv_error_info_subid_v(error_info), pri_ringstation_sys_priv_error_info_priv_level_v(error_info), @@ -158,50 +158,52 @@ void gp10b_priv_ring_isr(struct gk20a *g) if (status1 != 0U) { gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE); for (gpc = 0; gpc < g->ops.priv_ring.get_gpc_count(g); gpc++) { - offset = gpc * gpc_stride; - if ((status1 & BIT32(gpc)) != 0U) { - error_info = gk20a_readl(g, - pri_ringstation_gpc_gpc0_priv_error_info_r() + offset); - error_code = gk20a_readl(g, - pri_ringstation_gpc_gpc0_priv_error_code_r() + offset); - nvgpu_err(g, "GPC%u write error. ADR 0x%08x " - "WRDAT 0x%08x " - "INFO 0x%08x (subid 0x%08x priv level %d), " - "CODE 0x%08x", gpc, - gk20a_readl(g, - pri_ringstation_gpc_gpc0_priv_error_adr_r() + offset), - gk20a_readl(g, - pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + offset), - error_info, - pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info), - pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), - error_code); + if ((status1 & BIT32(gpc)) == 0U) { + continue; + } + gpc_offset = gpc * gpc_stride; + error_info = nvgpu_readl(g, + pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc_offset); + error_code = nvgpu_readl(g, + pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc_offset); + nvgpu_err(g, "GPC%u write error. ADR 0x%08x " + "WRDAT 0x%08x " + "INFO 0x%08x (subid 0x%08x priv level %d), " + "CODE 0x%08x", gpc, + nvgpu_readl(g, + pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc_offset), + nvgpu_readl(g, + pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc_offset), + error_info, + pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info), + pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), + error_code); - if (g->ops.priv_ring.decode_error_code != NULL) { - g->ops.priv_ring.decode_error_code(g, - error_code); - } + if (g->ops.priv_ring.decode_error_code != NULL) { + g->ops.priv_ring.decode_error_code(g, error_code); + } - status1 = status1 & (~(BIT(gpc))); - if (status1 == 0U) { - break; - } + status1 = status1 & (~(BIT(gpc))); + if (status1 == 0U) { + break; } } } /* clear interrupt */ - cmd = gk20a_readl(g, pri_ringmaster_command_r()); + cmd = nvgpu_readl(g, pri_ringmaster_command_r()); cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), pri_ringmaster_command_cmd_ack_interrupt_f()); - gk20a_writel(g, pri_ringmaster_command_r(), cmd); + nvgpu_writel(g, pri_ringmaster_command_r(), cmd); /* poll for clear interrupt done */ + retry = GP10B_PRIV_RING_POLL_CLEAR_INTR_RETRIES; + cmd = pri_ringmaster_command_cmd_v( - gk20a_readl(g, pri_ringmaster_command_r())); + nvgpu_readl(g, pri_ringmaster_command_r())); while ((cmd != pri_ringmaster_command_cmd_no_cmd_v()) && (retry != 0)) { - nvgpu_udelay(20); + nvgpu_udelay(GP10B_PRIV_RING_POLL_CLEAR_INTR_UDELAY); cmd = pri_ringmaster_command_cmd_v( - gk20a_readl(g, pri_ringmaster_command_r())); + nvgpu_readl(g, pri_ringmaster_command_r())); retry--; } diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.h similarity index 84% rename from drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h rename to drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.h index db96ec04d..37edd9f3f 100644 --- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h +++ b/drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b.h @@ -1,7 +1,7 @@ /* * GP10B PRIV ringmaster * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -26,8 +26,10 @@ struct gk20a; +#define GP10B_PRIV_RING_POLL_CLEAR_INTR_RETRIES 100 +#define GP10B_PRIV_RING_POLL_CLEAR_INTR_UDELAY 20 + void gp10b_priv_ring_isr(struct gk20a *g); -void gp10b_priv_ring_decode_error_code(struct gk20a *g, - u32 error_code); +void gp10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code); #endif /* NVGPU_PRIV_RING_GP10B_H */ diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 6f94b3596..61844b9c9 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -26,9 +26,9 @@ #include "hal/bus/bus_gp10b.h" #include "hal/bus/bus_gv100.h" #include "hal/bus/bus_tu104.h" +#include "hal/priv_ring/priv_ring_gm20b.h" +#include "hal/priv_ring/priv_ring_gp10b.h" -#include "common/priv_ring/priv_ring_gm20b.h" -#include "common/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/tu104_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gm20b.h"