From 0a25376965120c11f91962970147c045b6ed6b1f Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 14 Apr 2021 17:01:42 +0530 Subject: [PATCH] gpu: nvgpu: disable access to PE unit when MIG is enabled PE unit belongs to GR pipeline but not compute. Hence disabled access to the PE register in the GR Boot flow to prevent following PRIV error when SMC mode is enabled. PRI timeout: ADR 0x00503018 READ DATA 0x00000000 FECS_ERRCODE 0xbadf1100 [Error Type]: decode error Jira NVGPU-6699 Change-Id: Ia6f58258611a010252c7ead46b1b48cbf1b64001 Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2514894 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Lakshmanan M Reviewed-by: Deepak Nibade Reviewed-by: svc-mobile-misra Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 46c4934d6..7637f52d9 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -232,7 +232,9 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr) g->ops.gr.init.gpc_mmu(g); - g->ops.gr.init.pes_vsc_stream(g); + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { + g->ops.gr.init.pes_vsc_stream(g); + } if (g->ops.priv_ring.set_ppriv_timeout_settings != NULL) { g->ops.priv_ring.set_ppriv_timeout_settings(g);