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gpu: nvgpu: unit: add io callbacks for tegra fuses

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Remove WAR to set FMODEL during gv11b_init_hal.
Instead, add io callbacks for tegra fuses, and return
GCPLEX_CONFIG_WPR_ENABLED_MASK for FUSE_GCPLEX_CONFIG_FUSE_0.

Jira NVGPU-3476

Change-Id: I0739d66668b0f5c6658346b67bc368682edda4da
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120680
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-05-16 18:08:03 -07:00
committed by mobile promotions
parent 77a5d43365
commit 0a2bac5974
7 changed files with 105 additions and 12 deletions
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15
userspace/units/fifo/nvgpu-fifo-gv11b.c
View File

@@ -27,9 +27,12 @@
#include <unit/unit.h>
#include <nvgpu/posix/io.h>
#include <nvgpu/posix/soc_fuse.h>
#include <nvgpu/gk20a.h>
#include "hal/fuse/fuse_gm20b.h"
#include "nvgpu-fifo-gv11b.h"
u32 gv11b_fuse_regs[] = {
@@ -13490,6 +13493,14 @@ static void readl_access_reg_fn(struct gk20a *g,
access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
}
static int tegra_fuse_readl_access_reg_fn(unsigned long offset, u32 *value)
{
if (offset == FUSE_GCPLEX_CONFIG_FUSE_0) {
*value = GCPLEX_CONFIG_WPR_ENABLED_MASK;
}
return 0;
}
static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
/* Write APIs all can use the same accessor. */
.writel = writel_access_reg_fn,
@@ -13501,6 +13512,8 @@ static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
.__readl = readl_access_reg_fn,
.readl = readl_access_reg_fn,
.bar1_readl = readl_access_reg_fn,
.tegra_fuse_readl = tegra_fuse_readl_access_reg_fn,
};
int test_fifo_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
@@ -13583,7 +13596,7 @@ clean_up_top:
nvgpu_posix_io_unregister_reg_space(g, &gv11b_top_reg_space);
clean_up_master:
nvgpu_posix_io_unregister_reg_space(g, &gv11b_master_reg_space);
return UNIT_FAIL;
return -ENOMEM;
}
void test_fifo_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)

9
userspace/units/fifo/tsg/nvgpu-tsg.c
View File

@@ -31,6 +31,7 @@
#include <nvgpu/tsg.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/fifo/userd.h>
#include <nvgpu/fuse.h>
#include "hal/fifo/tsg_gk20a.h"
@@ -86,14 +87,8 @@ static int test_fifo_init_support(struct unit_module *m,
goto fail;
}
/*
* set IS_FMODEL to avoid reading fuses
* TODO: add fuses reg space to avoid this
*/
nvgpu_set_enabled(g, NVGPU_IS_FMODEL, true);
gv11b_init_hal(g);
g->ops.fifo.init_fifo_setup_hw = NULL;
nvgpu_set_enabled(g, NVGPU_IS_FMODEL, false);
#ifdef NVGPU_USERD
/*
@@ -140,7 +135,7 @@ static int test_tsg_release(struct unit_module *m,
struct test_tsg_args *t = args;
if (t->tsg == NULL) {
unit_return_fail(m, "tsg in NULL");
unit_return_fail(m, "tsg is NULL");
}
nvgpu_ref_put(&t->tsg->refcount, nvgpu_tsg_release);