gpu: nvgpu: use explicit phys address for pci simulation

nvgpu_mem_get_addr() gets virtual/phys address depending on the platform.
But we need to explicitly use physical addresses to configure PCI simulation
support since simulator expects physical address only

Hence use nvgpu_mem_get_phys_addr() explicitly to configure msg/send/recv
buffers needed for pci simulation support

Jira NVGPUT-41

Change-Id: I6870feef35fe81d43189fa048dc2f7052926bcc4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-06-21 03:03:59 -07:00
committed by mobile promotions
parent e323f562b2
commit 0a939d12f4

View File

@@ -89,11 +89,11 @@ static int rpc_send_message(struct gk20a *g)
sim_dma_target_phys_pci_coherent_f() |
sim_dma_status_valid_f() |
sim_dma_size_4kb_f() |
sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &g->sim->msg_bfr)
sim_dma_addr_lo_f(nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr)
>> PAGE_SHIFT);
*sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) =
u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr));
u64_hi32(nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr));
*sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++;
@@ -138,7 +138,8 @@ static int rpc_recv_poll(struct gk20a *g)
recv_phys_addr = (u64)recv_phys_addr_hi << 32 |
(u64)recv_phys_addr_lo << PAGE_SHIFT;
if (recv_phys_addr != nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) {
if (recv_phys_addr !=
nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr)) {
nvgpu_err(g, "Error in RPC reply");
return -EINVAL;
}
@@ -217,7 +218,7 @@ static void nvgpu_sim_init_late(struct gk20a *g)
sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put);
/* write send ring address and make it valid */
phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr);
phys = nvgpu_mem_get_phys_addr(g, &g->sim->send_bfr);
sim_writel(g->sim, sim_send_ring_hi_r(),
sim_send_ring_hi_addr_f(u64_hi32(phys)));
sim_writel(g->sim, sim_send_ring_r(),
@@ -234,7 +235,7 @@ static void nvgpu_sim_init_late(struct gk20a *g)
sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get);
/* write send ring address and make it valid */
phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr);
phys = nvgpu_mem_get_phys_addr(g, &g->sim->recv_bfr);
sim_writel(g->sim, sim_recv_ring_hi_r(),
sim_recv_ring_hi_addr_f(u64_hi32(phys)));
sim_writel(g->sim, sim_recv_ring_r(),