From 0b81ed7530b246b4ecc784ac841f35871b4c41e5 Mon Sep 17 00:00:00 2001 From: Scott Long Date: Thu, 8 Nov 2018 20:17:11 -0800 Subject: [PATCH] gpu: nvgpu: nvgpu_memcpy changes to sim code MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs to qualified/unqualified types. To circumvent this issue we've introduced a new MISRA-compliant nvgpu_memcpy() function. While sim code does not need to be MISRA-compliant this change switches over all memcpy() uses to nvgpu_memcpy() with appropriate casts applied to maintain consistency within the nvgpu source base. JIRA NVGPU-849 Change-Id: Ie0313e2902fffe2acfca714a2ced034406258a75 Signed-off-by: Scott Long Reviewed-on: https://git-master.nvidia.com/r/1946264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/sim.c | 3 ++- drivers/gpu/nvgpu/common/sim_pci.c | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/sim.c b/drivers/gpu/nvgpu/common/sim.c index f361d10fa..b94afef6f 100644 --- a/drivers/gpu/nvgpu/common/sim.c +++ b/drivers/gpu/nvgpu/common/sim.c @@ -30,6 +30,7 @@ #include #include #include +#include int nvgpu_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem) { @@ -233,7 +234,7 @@ static void nvgpu_sim_esc_readl(struct gk20a *g, err = issue_rpc_and_wait(g); if (err == 0) { - (void) memcpy(data, sim_msg_param(g, data_offset), + nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g, data_offset), sizeof(u32)); } else { *data = 0xffffffff; diff --git a/drivers/gpu/nvgpu/common/sim_pci.c b/drivers/gpu/nvgpu/common/sim_pci.c index 75f58e114..a12b44224 100644 --- a/drivers/gpu/nvgpu/common/sim_pci.c +++ b/drivers/gpu/nvgpu/common/sim_pci.c @@ -29,6 +29,7 @@ #include #include #include +#include static inline u32 sim_msg_header_size(void) { @@ -201,7 +202,8 @@ static void nvgpu_sim_esc_readl(struct gk20a *g, err = issue_rpc_and_wait(g); if (err == 0) { - (void) memcpy(data, sim_msg_param(g, data_offset + 0xc), + nvgpu_memcpy((u8 *)data, + (u8 *)sim_msg_param(g, data_offset + 0xc), sizeof(u32)); } else { *data = 0xffffffff;