diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobj.c b/drivers/gpu/nvgpu/common/boardobj/boardobj.c
index 0a20c5534..3974679dc 100644
--- a/drivers/gpu/nvgpu/common/boardobj/boardobj.c
+++ b/drivers/gpu/nvgpu/common/boardobj/boardobj.c
@@ -49,7 +49,7 @@ int boardobj_construct_super(struct gk20a *g, struct boardobj **ppboardobj,
 	pboardobj->g = g;
 	pboardobj->type = devtmp->type;
 	pboardobj->idx = CTRL_BOARDOBJ_IDX_INVALID;
-	pboardobj->type_mask   = BIT(pboardobj->type) | devtmp->type_mask;
+	pboardobj->type_mask   = BIT32(pboardobj->type) | devtmp->type_mask;
 
 	pboardobj->implements  = boardobj_implements_super;
 	pboardobj->destruct    = boardobj_destruct_super;
diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
index 585b4c835..0b7829e2f 100644
--- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
+++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
 *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -970,6 +970,7 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g,
 	struct pmu_cmd cmd;
 	u32 seqdesc;
 	int status = 0;
+	size_t tmp_size;
 
 	nvgpu_log_info(g, " ");
 
@@ -977,8 +978,10 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g,
 	(void) memset(&handlerparams, 0, sizeof(handlerparams));
 	(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
 	cmd.hdr.unit_id	= pboardobjgrp->pmu.unitid;
-	cmd.hdr.size = sizeof(struct nv_pmu_boardobj_cmd_grp) +
+	tmp_size = sizeof(struct nv_pmu_boardobj_cmd_grp) +
 					sizeof(struct pmu_hdr);
+	nvgpu_assert(tmp_size <= (size_t)U8_MAX);
+	cmd.hdr.size = U8(tmp_size);
 
 	pgrpcmd  = &cmd.cmd.boardobj.grp;
 	pgrpcmd->cmd_type = pcmd->id;
@@ -998,7 +1001,7 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g,
 	 * but PMU access pmu boardobjgrp data from vidmem copied above
 	 */
 	payload.in.buf = pcmd->buf;
-	payload.in.size = max(pcmd->hdrsize, pcmd->entrysize);
+	payload.in.size = U32(max(pcmd->hdrsize, pcmd->entrysize));
 	payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
 	payload.in.offset = offsetof(struct nv_pmu_boardobj_cmd_grp, grp);
 
diff --git a/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c b/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c
index 63ecf3938..48e93b02a 100644
--- a/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c
+++ b/drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c
@@ -236,7 +236,7 @@ int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx)
 	index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
 	offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
 
-	mask->data[index] &= ~BIT(offset);
+	mask->data[index] &= ~BIT32(offset);
 
 	return 0;
 }
@@ -256,7 +256,7 @@ int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx)
 	index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
 	offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
 
-	mask->data[index] |= BIT(offset);
+	mask->data[index] |= BIT32(offset);
 
 	return 0;
 }
@@ -276,7 +276,7 @@ int boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx)
 	index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
 	offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
 
-	mask->data[index] ^= ~BIT(offset);
+	mask->data[index] ^= ~BIT32(offset);
 
 	return 0;
 }