diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
index 4b8e61c4e..67f9b5320 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
@@ -176,10 +176,13 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
 	struct fifo_gk20a *f = &g->fifo;
 	u32 chid;
 	unsigned int i;
+	u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
+	u32 host_num_engines = nvgpu_get_litter_value(g,
+					 GPU_LIT_HOST_NUM_ENGINES);
 
 	struct ch_state **ch_state;
 
-	for (i = 0; i < fifo_pbdma_status__size_1_v(); i++) {
+	for (i = 0; i < host_num_pbdma; i++) {
 		u32 status = gk20a_readl(g, fifo_pbdma_status_r(i));
 		u32 chan_status = fifo_pbdma_status_chan_status_v(status);
 
@@ -204,7 +207,7 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
 	}
 	gk20a_debug_output(o, "\n");
 
-	for (i = 0; i < fifo_engine_status__size_1_v(); i++) {
+	for (i = 0; i < host_num_engines; i++) {
 		u32 status = gk20a_readl(g, fifo_engine_status_r(i));
 		u32 ctx_status = fifo_engine_status_ctx_status_v(status);
 
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 0d3a75fca..95351a43e 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -3115,9 +3115,11 @@ bool gk20a_fifo_mmu_fault_pending(struct gk20a *g)
 
 bool gk20a_fifo_is_engine_busy(struct gk20a *g)
 {
-	unsigned int i;
+	u32 i, host_num_engines;
 
-	for (i = 0; i < fifo_engine_status__size_1_v(); i++) {
+	host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
+
+	for (i = 0; i < host_num_engines; i++) {
 		u32 status = gk20a_readl(g, fifo_engine_status_r(i));
 		if (fifo_engine_status_engine_v(status) ==
 			fifo_engine_status_engine_busy_v())
@@ -3131,14 +3133,17 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g)
 	struct nvgpu_timeout timeout;
 	unsigned long delay = GR_IDLE_CHECK_DEFAULT;
 	int ret = -ETIMEDOUT;
-	u32 i;
+	u32 i, host_num_engines;
 
 	gk20a_dbg_fn("");
 
+	host_num_engines =
+		 nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
+
 	nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
 			   NVGPU_TIMER_CPU_TIMER);
 
-	for (i = 0; i < fifo_engine_status__size_1_v(); i++) {
+	for (i = 0; i < host_num_engines; i++) {
 		do {
 			u32 status = gk20a_readl(g, fifo_engine_status_r(i));
 			if (!fifo_engine_status_engine_v(status)) {