From 0c23bf57ea95512946ca5ba48f204a7f86bce89f Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 16 Mar 2020 17:56:13 -0400 Subject: [PATCH] gpu: nvgpu: build flag for secure boot Use CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT build flag for gm20b_gr_falcon_fecs_host_int_enable. Jira NVGPU-4661 Change-Id: Id7d991b81206d00e38049556b42b4e9a4abd1708 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313620 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: automaticguardword Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Alex Waterman Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index deda36bd2..a5fff580b 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -227,7 +227,7 @@ void gm20b_gr_falcon_configure_fmodel(struct gk20a *g) */ /* Sideband mailbox writes are done a bit differently */ - +#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT void gm20b_gr_falcon_fecs_host_int_enable(struct gk20a *g) { nvgpu_writel(g, gr_fecs_host_int_enable_r(), @@ -237,3 +237,4 @@ void gm20b_gr_falcon_fecs_host_int_enable(struct gk20a *g) gr_fecs_host_int_enable_umimp_illegal_method_enable_f() | gr_fecs_host_int_enable_watchdog_enable_f()); } +#endif