diff --git a/drivers/gpu/nvgpu/common/linux/clk.c b/drivers/gpu/nvgpu/common/linux/clk.c
index a0e56455d..414b17c45 100644
--- a/drivers/gpu/nvgpu/common/linux/clk.c
+++ b/drivers/gpu/nvgpu/common/linux/clk.c
@@ -19,6 +19,7 @@
 #include <linux/clk.h>
 
 #include <soc/tegra/tegra-dvfs.h>
+#include <soc/tegra/tegra-bpmp-dvfs.h>
 
 #include "clk.h"
 #include "os_linux.h"
@@ -86,6 +87,8 @@ static int nvgpu_linux_clk_set_rate(struct gk20a *g,
 
 static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
 {
+	struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
+
 	/*
 	 * On Tegra platforms with GPCPLL bus (gbus) GPU tegra_clk clock exposed
 	 * to frequency governor is a shared user on the gbus. The latter can be
@@ -95,6 +98,10 @@ static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g)
 		return tegra_dvfs_get_fmax_at_vmin_safe_t(
 			clk_get_parent(g->clk.tegra_clk));
 
+	if (platform->maxmin_clk_id)
+		return tegra_bpmp_dvfs_get_fmax_at_vmin(
+			platform->maxmin_clk_id);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h
index dec79b870..cdb221eb0 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h
@@ -65,6 +65,7 @@ struct gk20a_platform {
 	 * for filling this data. */
 	struct clk *clk[GK20A_CLKS_MAX];
 	int num_clks;
+	int maxmin_clk_id;
 
 #ifdef CONFIG_RESET_CONTROLLER
 	/* Reset control for device */
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
index 08c5df0fd..df10e36c2 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c
@@ -24,6 +24,7 @@
 
 #include <soc/tegra/tegra_bpmp.h>
 #include <soc/tegra/tegra_powergate.h>
+#include <soc/tegra/tegra-bpmp-dvfs.h>
 
 #include <dt-bindings/memory/tegra-swgroup.h>
 
@@ -98,6 +99,13 @@ int gp10b_tegra_get_clocks(struct device *dev)
 	}
 	platform->num_clks = i;
 
+	if (platform->clk[0]) {
+		i = tegra_bpmp_dvfs_get_clk_id(dev->of_node,
+					       tegra_gp10b_clocks[0].name);
+		if (i > 0)
+			platform->maxmin_clk_id = i;
+	}
+
 	return 0;
 }