nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 01:50:07 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Cleanup the MMU fault print

Browse Source 
Make this print more informative and easier to pull information
from.

Change-Id: I59366f0cf58ca08ee2030c936c02c225f34515d6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1940519
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2018-10-31 14:24:30 -07:00
committed by mobile promotions
parent 61aab8dead
commit 0c8be8a596
1 changed files with 19 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1604,24 +1604,25 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
mmfault_info.client_type_desc, mmfault_info.client_type_desc,
mmfault_info.client_id_desc, mmfault_info.client_id_desc,
mmfault_info.fault_type_desc); mmfault_info.fault_type_desc);
nvgpu_err(g, "%s mmu fault on engine %d, " nvgpu_err(g, "MMU fault @ address: 0x%llx %s",
"engine subid %d (%s), client %d (%s), " mmfault_info.fault_addr,
"addr 0x%llx, type %d (%s), access_type 0x%08x," fake_fault ? "[FAKE]" : "");
"inst_ptr 0x%llx", nvgpu_err(g, " Engine: %d subid: %d (%s)",
fake_fault ? "fake" : "", (int)engine_id,
engine_id, mmfault_info.client_type,
mmfault_info.client_type, mmfault_info.client_type_desc);
mmfault_info.client_type_desc, nvgpu_err(g, " Client %d (%s), ",
mmfault_info.client_id, mmfault_info.client_id_desc, mmfault_info.client_id,
mmfault_info.fault_addr, mmfault_info.client_id_desc);
mmfault_info.fault_type, nvgpu_err(g, " Type %d (%s); access_type 0x%08x; inst_ptr 0x%llx",
mmfault_info.fault_type_desc, mmfault_info.fault_type,
mmfault_info.access_type, mmfault_info.inst_ptr); mmfault_info.fault_type_desc,
mmfault_info.access_type, mmfault_info.inst_ptr);
if (ctxsw) { if (ctxsw) {
g->ops.gr.dump_gr_falcon_stats(g); g->ops.gr.dump_gr_falcon_stats(g);
nvgpu_err(g, "gr_status_r : 0x%x", nvgpu_err(g, " gr_status_r: 0x%x",
gk20a_readl(g, gr_status_r())); gk20a_readl(g, gr_status_r()));
} }
/* get the channel/TSG */ /* get the channel/TSG */
@@ -1652,7 +1653,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
refch = gk20a_channel_get(ch); refch = gk20a_channel_get(ch);
} }
} else { } else {
/* read channel based on instruction pointer */ /* Look up channel from the inst block pointer. */
ch = gk20a_refch_from_inst_ptr(g, ch = gk20a_refch_from_inst_ptr(g,
mmfault_info.inst_ptr); mmfault_info.inst_ptr);
refch = ch; refch = ch;
@@ -1731,9 +1732,8 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
} }
gk20a_channel_put(ch); gk20a_channel_put(ch);
} else { } else {
nvgpu_err(g, nvgpu_err(g, "mmu error in freed channel %d",
"mmu error in freed channel %d", ch->chid);
ch->chid);
} }
} else if (mmfault_info.inst_ptr == } else if (mmfault_info.inst_ptr ==
nvgpu_inst_block_addr(g, &g->mm.bar1.inst_block)) { nvgpu_inst_block_addr(g, &g->mm.bar1.inst_block)) {