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gpu: nvgpu: add characteristic flag for syncpoint address support
Add characteristic flag NVGPU_GPU_FLAGS_SUPPORT_SYNCPOINT_ADDRESS to indicate if platform supports semaphore GPU_VA address for a syncpoint Define NVGPU_SUPPORT_SYNCPOINT_ADDRESS for core driver book keeping Set this flag for both GV100 and GV11B since Xavier SoC supports a semaphore GPU_VA address for a syncpoint through syncpoint SHIM Bug 200327559 Change-Id: I1f31673c9fd59f493d0b35a80d23151fc063ae06 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1649364 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -156,6 +156,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
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NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL},
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NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL},
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{NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS,
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{NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS,
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NVGPU_SUPPORT_DETERMINISTIC_OPTS},
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NVGPU_SUPPORT_DETERMINISTIC_OPTS},
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{NVGPU_GPU_FLAGS_SUPPORT_SYNCPOINT_ADDRESS,
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NVGPU_SUPPORT_SYNCPOINT_ADDRESS},
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{NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE,
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{NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE,
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NVGPU_SUPPORT_IO_COHERENCE},
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NVGPU_SUPPORT_IO_COHERENCE},
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{NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST,
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{NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST,
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@@ -248,6 +248,7 @@ int gv100_init_gpu_characteristics(struct gk20a *g)
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return err;
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return err;
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
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return 0;
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return 0;
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}
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}
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@@ -154,5 +154,6 @@ int gv11b_init_gpu_characteristics(struct gk20a *g)
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_SCG, true);
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__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
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return 0;
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return 0;
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}
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}
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@@ -152,10 +152,14 @@ struct gk20a;
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#define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63
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#define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63
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/* Simultaneous Compute and Graphics (SCG) is available */
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/* Simultaneous Compute and Graphics (SCG) is available */
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#define NVGPU_SUPPORT_SCG 64
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#define NVGPU_SUPPORT_SCG 64
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/* GPU_VA address of a syncpoint is supported */
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#define NVGPU_SUPPORT_SYNCPOINT_ADDRESS 65
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/*
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/*
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* Must be greater than the largest bit offset in the above list.
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* Must be greater than the largest bit offset in the above list.
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*/
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*/
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#define NVGPU_MAX_ENABLED_BITS 65
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#define NVGPU_MAX_ENABLED_BITS 66
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/**
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/**
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* nvgpu_is_enabled - Check if the passed flag is enabled.
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* nvgpu_is_enabled - Check if the passed flag is enabled.
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@@ -154,6 +154,8 @@ struct nvgpu_gpu_zbc_query_table_args {
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#define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS (1ULL << 24)
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#define NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_OPTS (1ULL << 24)
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/* SCG support is available */
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/* SCG support is available */
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#define NVGPU_GPU_FLAGS_SUPPORT_SCG (1ULL << 25)
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#define NVGPU_GPU_FLAGS_SUPPORT_SCG (1ULL << 25)
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/* GPU_VA address of a syncpoint is supported */
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#define NVGPU_GPU_FLAGS_SUPPORT_SYNCPOINT_ADDRESS (1ULL << 26)
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/* SM LRF ECC is enabled */
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/* SM LRF ECC is enabled */
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#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
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#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
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/* SM SHM ECC is enabled */
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/* SM SHM ECC is enabled */
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