diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c index 3eda929f5..e77f05725 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c +++ b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.c @@ -32,15 +32,10 @@ #include #include #include -#include -#include -#include #include #include #include -#include "gm20b/mm_gm20b.h" - #include "pmu_gm20b.h" #include "acr_gm20b.h" @@ -78,11 +73,6 @@ void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) g->ops.fb.read_wpr_info(g, inf); } -bool gm20b_is_pmu_supported(struct gk20a *g) -{ - return true; -} - static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) { struct nvgpu_pmu *pmu = &g->pmu; diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.h b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.h index 0e4b6cf07..fe7809e78 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gm20b.h +++ b/drivers/gpu/nvgpu/common/pmu/acr_gm20b.h @@ -25,15 +25,9 @@ #ifndef NVGPU_GM20B_ACR_GM20B_H #define NVGPU_GM20B_ACR_GM20B_H -#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin" -#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin" -#define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin" -#define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin" -#define GM20B_PMU_UCODE_SIG "pmu_sig.bin" #define GM20B_FECS_UCODE_SIG "fecs_sig.bin" #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin" -bool gm20b_is_pmu_supported(struct gk20a *g); int prepare_ucode_blob(struct gk20a *g); int acr_ucode_patch_sig(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gv11b.c b/drivers/gpu/nvgpu/common/pmu/acr_gv11b.c index 6fa747ceb..7e653eef6 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gv11b.c +++ b/drivers/gpu/nvgpu/common/pmu/acr_gv11b.c @@ -21,72 +21,19 @@ */ #include -#include -#include -#include #include -#include -#include #include -#include #include -#include -#include -#include #include #include -#include "gm20b/mm_gm20b.h" - -#include "acr_gv11b.h" -#include "pmu_gv11b.h" #include "pmu_gm20b.h" #include "acr_gm20b.h" #include "acr_gp106.h" +#include "acr_gv11b.h" -#include - -/*Defines*/ -#define gv11b_dbg_pmu(g, fmt, arg...) \ - nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) - -/*Externs*/ - -/*Forwards*/ - -void gv11b_setup_apertures(struct gk20a *g) -{ - struct mm_gk20a *mm = &g->mm; - struct nvgpu_mem *inst_block = &mm->pmu.inst_block; - - nvgpu_log_fn(g, " "); - - /* setup apertures - virtual */ - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), - pwr_fbif_transcfg_mem_type_physical_f() | - nvgpu_aperture_mask(g, inst_block, - pwr_fbif_transcfg_target_noncoherent_sysmem_f(), - pwr_fbif_transcfg_target_coherent_sysmem_f(), - pwr_fbif_transcfg_target_local_fb_f())); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), - pwr_fbif_transcfg_mem_type_virtual_f()); - /* setup apertures - physical */ - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), - pwr_fbif_transcfg_mem_type_physical_f() | - nvgpu_aperture_mask(g, inst_block, - pwr_fbif_transcfg_target_noncoherent_sysmem_f(), - pwr_fbif_transcfg_target_coherent_sysmem_f(), - pwr_fbif_transcfg_target_local_fb_f())); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_coherent_sysmem_f()); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_noncoherent_sysmem_f()); -} - -int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr, - struct hs_acr *acr_desc, bool is_recovery) +static int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, + struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery) { struct nvgpu_firmware *acr_fw = acr_desc->acr_fw; struct acr_fw_header *acr_fw_hdr = NULL; diff --git a/drivers/gpu/nvgpu/common/pmu/acr_gv11b.h b/drivers/gpu/nvgpu/common/pmu/acr_gv11b.h index 5c6fafd19..fcaf71830 100644 --- a/drivers/gpu/nvgpu/common/pmu/acr_gv11b.h +++ b/drivers/gpu/nvgpu/common/pmu/acr_gv11b.h @@ -23,14 +23,7 @@ #ifndef NVGPU_ACR_GV11B_H #define NVGPU_ACR_GV11B_H - -int gv11b_bootstrap_hs_flcn(struct gk20a *g); -int gv11b_init_pmu_setup_hw1(struct gk20a *g, - void *desc, u32 bl_sz); -void gv11b_setup_apertures(struct gk20a *g); - void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); -int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr, - struct hs_acr *acr_desc, bool is_recovery); + #endif /* NVGPU_ACR_GV11B_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c index 2e0269547..22781a76b 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c @@ -411,3 +411,8 @@ void gm20b_secured_pmu_start(struct gk20a *g) gk20a_writel(g, pwr_falcon_cpuctl_alias_r(), pwr_falcon_cpuctl_startcpu_f(1)); } + +bool gm20b_is_pmu_supported(struct gk20a *g) +{ + return true; +} diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.h b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.h index 0e4968fbd..8303682bd 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gm20b.h @@ -41,4 +41,5 @@ int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g, struct hs_acr *acr_desc, struct nvgpu_falcon_bl_info *bl_info); void gm20b_secured_pmu_start(struct gk20a *g); +bool gm20b_is_pmu_supported(struct gk20a *g); #endif /*NVGPU_GM20B_PMU_GM20B_H*/ diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c b/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c index 5694515ae..ea13d7a58 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.c @@ -509,3 +509,34 @@ int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) return 0; } + +void gv11b_setup_apertures(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + struct nvgpu_mem *inst_block = &mm->pmu.inst_block; + + nvgpu_log_fn(g, " "); + + /* setup apertures - virtual */ + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), + pwr_fbif_transcfg_mem_type_physical_f() | + nvgpu_aperture_mask(g, inst_block, + pwr_fbif_transcfg_target_noncoherent_sysmem_f(), + pwr_fbif_transcfg_target_coherent_sysmem_f(), + pwr_fbif_transcfg_target_local_fb_f())); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), + pwr_fbif_transcfg_mem_type_virtual_f()); + /* setup apertures - physical */ + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), + pwr_fbif_transcfg_mem_type_physical_f() | + nvgpu_aperture_mask(g, inst_block, + pwr_fbif_transcfg_target_noncoherent_sysmem_f(), + pwr_fbif_transcfg_target_coherent_sysmem_f(), + pwr_fbif_transcfg_target_local_fb_f())); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_coherent_sysmem_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_noncoherent_sysmem_f()); +} diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.h b/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.h index 5bca14f26..d941c7670 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/common/pmu/pmu_gv11b.h @@ -35,4 +35,5 @@ int gv11b_pmu_setup_elpg(struct gk20a *g); u32 gv11b_pmu_get_irqdest(struct gk20a *g); void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0); +void gv11b_setup_apertures(struct gk20a *g); #endif /* NVGPU_PMU_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h index 55d5a5ebd..b59315dd0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h @@ -176,9 +176,6 @@ struct nvgpu_acr { struct hs_acr acr_ahesasc; struct hs_acr acr_asb; - struct nvgpu_firmware *pmu_fw; - struct nvgpu_firmware *pmu_desc; - int (*prepare_ucode_blob)(struct gk20a *g); void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); int (*alloc_blob_space)(struct gk20a *g, size_t size,