From 0d5bcdf28bdc2c1ee64e6a9750b31a8b4b66422e Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 28 Apr 2021 17:50:40 +0530 Subject: [PATCH] gpu: nvgpu: disable access to regs in MIG mode The following registers belong to GR but are not a part of Sys-Compute Pipe. gr_pd_num_tpc_per_gpc_r gr_ds_num_tpc_per_gpc_r Jira NVGPU-6699 Change-Id: I350b0ea429f98845db4a31168a8dfb9211706c7a Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521784 Tested-by: mobile promotions Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: svcacv Reviewed-by: Lakshmanan M Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/gr/fs_state.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/fs_state.c b/drivers/gpu/nvgpu/common/gr/fs_state.c index 4fb3c2d4c..d6b2e0f91 100644 --- a/drivers/gpu/nvgpu/common/gr/fs_state.c +++ b/drivers/gpu/nvgpu/common/gr/fs_state.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -143,7 +143,9 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config) config, NULL, false); } - g->ops.gr.init.pd_tpc_per_gpc(g, config); + if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) { + g->ops.gr.init.pd_tpc_per_gpc(g, config); + } #ifdef CONFIG_NVGPU_GRAPHICS if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {