From 0e1e142aa93a2a8f67978e9fc80a0cc50fea6d13 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Thu, 25 Apr 2019 14:37:38 -0700 Subject: [PATCH] gpu: nvgpu: move pdb_cache_war to ramin HAL Removed dependency on ram tu104 hw header from fifo code. Moved the following HALs from fifo to ramin - init_pdb_cache_war - deinit_pdb_cache_war Jira NVGPU-2012 Change-Id: Ia1848c430b8d19861d92d14d3cd01c9119553002 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2105351 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.sources | 1 + drivers/gpu/nvgpu/common/mm/mm.c | 8 +- drivers/gpu/nvgpu/hal/fifo/ramin_tu104.c | 114 +++++++++++++++++++++++ drivers/gpu/nvgpu/hal/fifo/ramin_tu104.h | 33 +++++++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 5 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 4 +- drivers/gpu/nvgpu/tu104/fifo_tu104.c | 98 +------------------ drivers/gpu/nvgpu/tu104/fifo_tu104.h | 4 - 9 files changed, 159 insertions(+), 109 deletions(-) create mode 100644 drivers/gpu/nvgpu/hal/fifo/ramin_tu104.c create mode 100644 drivers/gpu/nvgpu/hal/fifo/ramin_tu104.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 931e81bce..30e27234f 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -279,6 +279,7 @@ nvgpu-y += \ hal/fifo/ramin_gm20b.o \ hal/fifo/ramin_gp10b.o \ hal/fifo/ramin_gv11b.o \ + hal/fifo/ramin_tu104.o \ hal/fifo/runlist_gk20a.o \ hal/fifo/runlist_gv11b.o \ hal/fifo/runlist_gv100.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 88b059168..971f63954 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -387,6 +387,7 @@ srcs += common/sim/sim.c \ hal/fifo/ramin_gm20b.c \ hal/fifo/ramin_gp10b.c \ hal/fifo/ramin_gv11b.c \ + hal/fifo/ramin_tu104.c \ hal/fifo/runlist_gk20a.c \ hal/fifo/runlist_gv11b.c \ hal/fifo/runlist_gv100.c \ diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index a471ec500..4231067e8 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c @@ -226,8 +226,8 @@ static void nvgpu_remove_mm_support(struct mm_gk20a *mm) nvgpu_vidmem_destroy(g); nvgpu_pd_cache_fini(g); - if (g->ops.fifo.deinit_pdb_cache_war != NULL) { - g->ops.fifo.deinit_pdb_cache_war(g); + if (g->ops.ramin.deinit_pdb_cache_war != NULL) { + g->ops.ramin.deinit_pdb_cache_war(g); } } @@ -585,8 +585,8 @@ static int nvgpu_init_mm_pdb_cache_war(struct gk20a *g) { int err; - if (g->ops.fifo.init_pdb_cache_war != NULL) { - err = g->ops.fifo.init_pdb_cache_war(g); + if (g->ops.ramin.init_pdb_cache_war != NULL) { + err = g->ops.ramin.init_pdb_cache_war(g); if (err != 0) { return err; } diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_tu104.c b/drivers/gpu/nvgpu/hal/fifo/ramin_tu104.c new file mode 100644 index 000000000..581de75ab --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_tu104.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "ramin_tu104.h" + +#include + +int tu104_ramin_init_pdb_cache_war(struct gk20a *g) +{ + u32 size = PAGE_SIZE * 258U; + u64 last_bind_pdb_addr; + u64 pdb_addr; + u32 pdb_addr_lo, pdb_addr_hi; + u32 i; + int err; + + if (nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) { + return 0; + } + + /* + * Allocate memory for 257 instance block binds + + * PDB bound to 257th instance block + */ + err = nvgpu_dma_alloc_sys(g, size, &g->pdb_cache_war_mem); + if (err != 0) { + return err; + } + + /* + * 257th instance block (i.e. last bind) needs to be bound to + * valid memory + * First 256 binds can happen to dummy addresses + */ + pdb_addr = PAGE_SIZE; + last_bind_pdb_addr = nvgpu_mem_get_addr(g, &g->pdb_cache_war_mem) + + (257U * PAGE_SIZE); + + /* Setup first 256 instance blocks */ + for (i = 0U; i < 256U; i++) { + pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); + pdb_addr_hi = u64_hi32(pdb_addr); + + nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, + ram_in_page_dir_base_lo_w() + (i * PAGE_SIZE / 4U), + nvgpu_aperture_mask(g, &g->pdb_cache_war_mem, + ram_in_page_dir_base_target_sys_mem_ncoh_f(), + ram_in_page_dir_base_target_sys_mem_coh_f(), + ram_in_page_dir_base_target_vid_mem_f()) | + ram_in_page_dir_base_vol_true_f() | + ram_in_big_page_size_64kb_f() | + ram_in_page_dir_base_lo_f(pdb_addr_lo) | + ram_in_use_ver2_pt_format_true_f()); + + nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, + ram_in_page_dir_base_hi_w() + (i * PAGE_SIZE / 4U), + ram_in_page_dir_base_hi_f(pdb_addr_hi)); + + pdb_addr += PAGE_SIZE; + } + + /* Setup 257th instance block */ + pdb_addr_lo = u64_lo32(last_bind_pdb_addr >> ram_in_base_shift_v()); + pdb_addr_hi = u64_hi32(last_bind_pdb_addr); + + nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, + ram_in_page_dir_base_lo_w() + (256U * PAGE_SIZE / 4U), + nvgpu_aperture_mask(g, &g->pdb_cache_war_mem, + ram_in_page_dir_base_target_sys_mem_ncoh_f(), + ram_in_page_dir_base_target_sys_mem_coh_f(), + ram_in_page_dir_base_target_vid_mem_f()) | + ram_in_page_dir_base_vol_true_f() | + ram_in_big_page_size_64kb_f() | + ram_in_page_dir_base_lo_f(pdb_addr_lo) | + ram_in_use_ver2_pt_format_true_f()); + + nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, + ram_in_page_dir_base_hi_w() + (256U * PAGE_SIZE / 4U), + ram_in_page_dir_base_hi_f(pdb_addr_hi)); + + return 0; +} + +void tu104_ramin_deinit_pdb_cache_war(struct gk20a *g) +{ + if (nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) { + nvgpu_dma_free(g, &g->pdb_cache_war_mem); + } +} diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_tu104.h b/drivers/gpu/nvgpu/hal/fifo/ramin_tu104.h new file mode 100644 index 000000000..2da5df641 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_tu104.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_RAMIN_TU104_H +#define NVGPU_RAMIN_TU104_H + +#include + +struct gk20a; + +int tu104_ramin_init_pdb_cache_war(struct gk20a *g); +void tu104_ramin_deinit_pdb_cache_war(struct gk20a *g); + +#endif /* NVGPU_RAMIN_TU104_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 03bab4c37..628a659ac 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -81,6 +81,7 @@ #include "hal/fifo/ramin_gm20b.h" #include "hal/fifo/ramin_gp10b.h" #include "hal/fifo/ramin_gv11b.h" +#include "hal/fifo/ramin_tu104.h" #include "hal/fifo/runlist_gk20a.h" #include "hal/fifo/runlist_gv11b.h" #include "hal/fifo/runlist_tu104.h" @@ -963,8 +964,6 @@ static const struct gpu_ops tu104_ops = { .intr_unset_recover_mask = gv11b_fifo_intr_unset_recover_mask, .setup_sw = nvgpu_fifo_setup_sw, .cleanup_sw = nvgpu_fifo_cleanup_sw, - .init_pdb_cache_war = tu104_init_pdb_cache_war, - .deinit_pdb_cache_war = tu104_deinit_pdb_cache_war, .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, .intr_0_enable = gv11b_fifo_intr_0_enable, .intr_1_enable = gk20a_fifo_intr_1_enable, @@ -1076,6 +1075,8 @@ static const struct gpu_ops tu104_ops = { .base_shift = gk20a_ramin_base_shift, .alloc_size = gk20a_ramin_alloc_size, .set_eng_method_buffer = gv11b_ramin_set_eng_method_buffer, + .init_pdb_cache_war = tu104_ramin_init_pdb_cache_war, + .deinit_pdb_cache_war = tu104_ramin_deinit_pdb_cache_war, }, .runlist = { .update_for_channel = gk20a_runlist_update_for_channel, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index a9a1ebf55..b2db21ed6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1007,8 +1007,6 @@ struct gpu_ops { struct mmu_fault_info *mmfault); void (*intr_set_recover_mask)(struct gk20a *g); void (*intr_unset_recover_mask)(struct gk20a *g); - int (*init_pdb_cache_war)(struct gk20a *g); - void (*deinit_pdb_cache_war)(struct gk20a *g); int (*set_sm_exception_type_mask)(struct channel_gk20a *ch, u32 exception_mask); struct { @@ -1062,6 +1060,8 @@ struct gpu_ops { struct nvgpu_mem *inst_block, struct nvgpu_mem *pdb_mem, bool replayable); + int (*init_pdb_cache_war)(struct gk20a *g); + void (*deinit_pdb_cache_war)(struct gk20a *g); void (*set_adr_limit)(struct gk20a *g, struct nvgpu_mem *inst_block, u64 va_limit); u32 (*base_shift)(void); diff --git a/drivers/gpu/nvgpu/tu104/fifo_tu104.c b/drivers/gpu/nvgpu/tu104/fifo_tu104.c index 21163f6cb..9726ff9ba 100644 --- a/drivers/gpu/nvgpu/tu104/fifo_tu104.c +++ b/drivers/gpu/nvgpu/tu104/fifo_tu104.c @@ -20,24 +20,12 @@ * DEALINGS IN THE SOFTWARE. */ -#include -#include -#include -#include -#include -#include +#include #include -#include #include "hal/fifo/fifo_gv11b.h" -#include "gk20a/fifo_gk20a.h" - #include "tu104/fifo_tu104.h" -#include "hal/func/func_tu104.h" - -#include -#include int tu104_init_fifo_setup_hw(struct gk20a *g) { @@ -47,87 +35,3 @@ int tu104_init_fifo_setup_hw(struct gk20a *g) return gv11b_init_fifo_setup_hw(g); } - -int tu104_init_pdb_cache_war(struct gk20a *g) -{ - u32 size = PAGE_SIZE * 258U; - u64 last_bind_pdb_addr; - u64 pdb_addr; - u32 pdb_addr_lo, pdb_addr_hi; - u32 i; - int err; - - if (nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) { - return 0; - } - - /* - * Allocate memory for 257 instance block binds + - * PDB bound to 257th instance block - */ - err = nvgpu_dma_alloc_sys(g, size, &g->pdb_cache_war_mem); - if (err != 0) { - return err; - } - - /* - * 257th instance block (i.e. last bind) needs to be bound to - * valid memory - * First 256 binds can happen to dummy addresses - */ - pdb_addr = PAGE_SIZE; - last_bind_pdb_addr = nvgpu_mem_get_addr(g, &g->pdb_cache_war_mem) + - (257U * PAGE_SIZE); - - /* Setup first 256 instance blocks */ - for (i = 0U; i < 256U; i++) { - pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); - pdb_addr_hi = u64_hi32(pdb_addr); - - nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_lo_w() + (i * PAGE_SIZE / 4U), - nvgpu_aperture_mask(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_target_sys_mem_ncoh_f(), - ram_in_page_dir_base_target_sys_mem_coh_f(), - ram_in_page_dir_base_target_vid_mem_f()) | - ram_in_page_dir_base_vol_true_f() | - ram_in_big_page_size_64kb_f() | - ram_in_page_dir_base_lo_f(pdb_addr_lo) | - ram_in_use_ver2_pt_format_true_f()); - - nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_hi_w() + (i * PAGE_SIZE / 4U), - ram_in_page_dir_base_hi_f(pdb_addr_hi)); - - pdb_addr += PAGE_SIZE; - } - - /* Setup 257th instance block */ - pdb_addr_lo = u64_lo32(last_bind_pdb_addr >> ram_in_base_shift_v()); - pdb_addr_hi = u64_hi32(last_bind_pdb_addr); - - nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_lo_w() + (256U * PAGE_SIZE / 4U), - nvgpu_aperture_mask(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_target_sys_mem_ncoh_f(), - ram_in_page_dir_base_target_sys_mem_coh_f(), - ram_in_page_dir_base_target_vid_mem_f()) | - ram_in_page_dir_base_vol_true_f() | - ram_in_big_page_size_64kb_f() | - ram_in_page_dir_base_lo_f(pdb_addr_lo) | - ram_in_use_ver2_pt_format_true_f()); - - nvgpu_mem_wr32(g, &g->pdb_cache_war_mem, - ram_in_page_dir_base_hi_w() + (256U * PAGE_SIZE / 4U), - ram_in_page_dir_base_hi_f(pdb_addr_hi)); - - return 0; -} - -void tu104_deinit_pdb_cache_war(struct gk20a *g) -{ - if (nvgpu_mem_is_valid(&g->pdb_cache_war_mem)) { - nvgpu_dma_free(g, &g->pdb_cache_war_mem); - } -} - diff --git a/drivers/gpu/nvgpu/tu104/fifo_tu104.h b/drivers/gpu/nvgpu/tu104/fifo_tu104.h index 9477d011a..815cd7005 100644 --- a/drivers/gpu/nvgpu/tu104/fifo_tu104.h +++ b/drivers/gpu/nvgpu/tu104/fifo_tu104.h @@ -26,11 +26,7 @@ #include struct gk20a; -struct channel_gk20a; int tu104_init_fifo_setup_hw(struct gk20a *g); -int tu104_init_pdb_cache_war(struct gk20a *g); -void tu104_deinit_pdb_cache_war(struct gk20a *g); - #endif /* NVGPU_FIFO_TU104_H */