From 0e2a013e3b9325c18b64c0e2f3525699c6875933 Mon Sep 17 00:00:00 2001 From: Vaibhav Kachore Date: Wed, 20 Feb 2019 11:32:45 +0530 Subject: [PATCH] gpu: nvgpu: write with ack for mailbox1 during fecs trace FECS ucode does a priv holdoff around the assertion of context reset. So, priv transactions (e.g. mailbox1 register write) might fail due to this. Hence, do write with ack i.e. write and read it back to make sure write happened for mailbox1. Bug 200417403 Change-Id: I463be1cb8fdd477106b87786cb0603327a22cebe Signed-off-by: Vaibhav Kachore Reviewed-on: https://git-master.nvidia.com/r/2023494 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index 8e55e8ab2..e1f9db15f 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c @@ -266,6 +266,17 @@ int gk20a_fecs_trace_poll(struct gk20a *g) nvgpu_wmb(); gk20a_fecs_trace_set_read_index(g, read); + /* + * FECS ucode does a priv holdoff around the assertion of context + * reset. So, pri transactions (e.g. mailbox1 register write) might + * fail due to this. Hence, do write with ack i.e. write and read + * it back to make sure write happened for mailbox1. + */ + while (gk20a_fecs_trace_get_read_index(g) != read) { + nvgpu_log(g, gpu_dbg_ctxsw, "mailbox1 update failed"); + gk20a_fecs_trace_set_read_index(g, read); + } + done: nvgpu_mutex_release(&trace->poll_lock); gk20a_idle(g);