From 0e367046e9b372272eb9f92cbd6c96c02d475670 Mon Sep 17 00:00:00 2001 From: Nicolas Benech Date: Wed, 10 Oct 2018 11:52:01 -0400 Subject: [PATCH] gpu: nvgpu: posix: Use nvgpu_mem_sgl for SGLs Initially, SGL functions were using nvgpu_mem behind the scenes which is inconvenient to actually use as a list. Instead, this patch uses the nvgpu_mem_sgl. JIRA NVGPU-1280 Change-Id: I251bf25e6133ac0d4ff8e44d86f634383978ea9a Signed-off-by: Nicolas Benech Reviewed-on: https://git-master.nvidia.com/r/1923712 Reviewed-by: Konsta Holtta Reviewed-by: Philip Elcan GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c | 31 ++++++++++++++------ 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c b/drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c index 26770e475..502cd1c38 100644 --- a/drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c +++ b/drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c @@ -25,6 +25,9 @@ #include #include #include +#include + +#define DMA_ERROR_CODE (~(u64)0x0) /* * These functions are somewhat meaningless. @@ -41,36 +44,46 @@ u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem) static struct nvgpu_sgl *nvgpu_mem_sgl_next(struct nvgpu_sgl *sgl) { - return NULL; + struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl; + + return (struct nvgpu_sgl *) mem->next; } static u64 nvgpu_mem_sgl_phys(struct gk20a *g, struct nvgpu_sgl *sgl) { - struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl; + struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl; - return (u64)(uintptr_t)mem->cpu_va; + return (u64)(uintptr_t)mem->phys; } static u64 nvgpu_mem_sgl_dma(struct nvgpu_sgl *sgl) { - struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl; + struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl; - return (u64)(uintptr_t)mem->cpu_va; + return (u64)(uintptr_t)mem->dma; } static u64 nvgpu_mem_sgl_length(struct nvgpu_sgl *sgl) { - struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl; + struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl; - return (u64)mem->aligned_size; + return (u64)mem->length; } static u64 nvgpu_mem_sgl_gpu_addr(struct gk20a *g, struct nvgpu_sgl *sgl, struct nvgpu_gmmu_attrs *attrs) { - struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl; + struct nvgpu_mem_sgl *mem = (struct nvgpu_mem_sgl *)sgl; - return mem->gpu_va; + if (mem->dma == 0U) { + return g->ops.mm.gpu_phys_addr(g, attrs, mem->phys); + } + + if (mem->dma == DMA_ERROR_CODE) { + return 0x0; + } + + return nvgpu_mem_iommu_translate(g, mem->dma); } static bool nvgpu_mem_sgt_iommuable(struct gk20a *g, struct nvgpu_sgt *sgt)