diff --git a/drivers/gpu/nvgpu/common/grmgr/grmgr.c b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
index 86be2580c..732e34031 100644
--- a/drivers/gpu/nvgpu/common/grmgr/grmgr.c
+++ b/drivers/gpu/nvgpu/common/grmgr/grmgr.c
@@ -473,3 +473,30 @@ u32 nvgpu_grmgr_get_gr_max_veid_count(struct gk20a *g, u32 gr_instance_id)
 
 	return nvgpu_grmgr_get_max_veid_count(g, gpu_instance_id);
 }
+
+u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id)
+{
+	u32 physical_gpc_mask = 0U;
+	u32 gpc_indx;
+	struct nvgpu_gpu_instance *gpu_instance;
+	struct nvgpu_gr_syspipe *gr_syspipe;
+	u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
+		g, gr_instance_id);
+
+	gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
+	gr_syspipe = &gpu_instance->gr_syspipe;
+
+	for (gpc_indx = 0U; gpc_indx < gr_syspipe->num_gpc; gpc_indx++) {
+		physical_gpc_mask |= BIT32(
+			gr_syspipe->gpcs[gpc_indx].physical_id);
+
+		nvgpu_log(g, gpu_dbg_mig,
+			"gpu_instance_id[%u] gr_instance_id[%u] gpc_indx[%u] "
+				"physical_gpc_id[%u] physical_gpc_mask[%x]",
+			gpu_instance_id, gr_instance_id, gpc_indx,
+			gr_syspipe->gpcs[gpc_indx].physical_id,
+			physical_gpc_mask);
+	}
+
+	return physical_gpc_mask;
+}
diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c b/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c
index 8f6c35e07..4f28ffcae 100644
--- a/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c
+++ b/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c
@@ -27,6 +27,7 @@
 #include <nvgpu/sec2/cmd.h>
 #include <nvgpu/gr/config.h>
 #include <nvgpu/gr/gr_utils.h>
+#include <nvgpu/gr/gr_instances.h>
 
 /* Add code below to handle SEC2 RTOS commands */
 /* LSF's bootstrap command */
@@ -49,12 +50,22 @@ static void sec2_handle_lsfm_boot_acr_msg(struct gk20a *g,
 
 static u32 get_gpc_falcon_idx_mask(struct gk20a *g)
 {
-	struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
-	u32 gpc_fs_mask = 0;
+	u32 gpc_falcon_idx_mask = 0U;
 
-	gpc_fs_mask = nvgpu_gr_config_get_gpc_mask(gr_config);
+	if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		gpc_falcon_idx_mask = nvgpu_grmgr_get_gr_physical_gpc_mask(g,
+			nvgpu_gr_get_cur_instance_id(g));
+	} else {
+		u32 gpc_fs_mask;
+		struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
 
-	return nvgpu_safe_sub_u32((1U << hweight32(gpc_fs_mask)), 1U);
+		gpc_fs_mask = nvgpu_gr_config_get_gpc_mask(gr_config);
+		gpc_falcon_idx_mask =
+			nvgpu_safe_sub_u32(
+			(1U << U32(hweight32(gpc_fs_mask))), 1U);
+	}
+
+	return gpc_falcon_idx_mask;
 }
 
 static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
@@ -80,7 +91,8 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
 	cmd.cmd.acr.bootstrap_falcon.flags = flags;
 	cmd.cmd.acr.bootstrap_falcon.falcon_id = falcon_id;
 	cmd.cmd.acr.bootstrap_falcon.falcon_instance =
-		LSF_FALCON_INSTANCE_DEFAULT;
+		nvgpu_grmgr_get_gr_syspipe_id(g,
+			nvgpu_gr_get_cur_instance_id(g));
 	cmd.cmd.acr.bootstrap_falcon.falcon_index_mask =
 		LSF_FALCON_INDEX_MASK_DEFAULT;
 
@@ -89,8 +101,11 @@ static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
 				get_gpc_falcon_idx_mask(g);
 	}
 
-	nvgpu_sec2_dbg(g, "NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON : %x",
-		falcon_id);
+	nvgpu_sec2_dbg(g, "NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON : %d "
+		"falcon_instance : %u falcon_index_mask : %x",
+		falcon_id,
+		cmd.cmd.acr.bootstrap_falcon.falcon_instance,
+		cmd.cmd.acr.bootstrap_falcon.falcon_index_mask);
 
 	command_ack = false;
 	err = nvgpu_sec2_cmd_post(g, &cmd, PMU_COMMAND_QUEUE_HPQ,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
index a0c89c4b0..178b7c437 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/grmgr.h
@@ -49,6 +49,7 @@ u32 nvgpu_grmgr_get_gr_instance_id_for_syspipe(struct gk20a *g,
 u32 nvgpu_grmgr_get_gpu_instance_max_veid_count(struct gk20a *g,
 		u32 gpu_instance_id);
 u32 nvgpu_grmgr_get_gr_max_veid_count(struct gk20a *g, u32 gr_instance_id);
+u32 nvgpu_grmgr_get_gr_physical_gpc_mask(struct gk20a *g, u32 gr_instance_id);
 
 static inline bool nvgpu_grmgr_is_mig_type_gpu_instance(
 		struct nvgpu_gpu_instance *gpu_instance)