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gpu: nvgpu: rename public channel unit APIs
Rename the public channel unit APIs to follow the convention of nvgpu_channel_*. gk20a_channel_deterministic_idle -> nvgpu_channel_deterministic_idle gk20a_channel_deterministic_unidle -> nvgpu_channel_deterministic_unidle gk20a_wait_until_counter_is_N -> nvgpu_channel_wait_until_counter_is_N nvgpu_gk20a_alloc_job -> nvgpu_channel_alloc_job Jira NVGPU-3248 Change-Id: I358d63d4e891f6d92c70efe887c07674bc0f9914 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123398 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -224,7 +224,7 @@ void nvgpu_channel_abort(struct nvgpu_channel *ch, bool channel_preempt)
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}
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}
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void gk20a_wait_until_counter_is_N(
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void nvgpu_channel_wait_until_counter_is_N(
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struct nvgpu_channel *ch, nvgpu_atomic_t *counter, int wait_value,
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struct nvgpu_cond *c, const char *caller, const char *counter_name)
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{
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@@ -307,7 +307,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force)
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/* wait until there's only our ref to the channel */
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if (!force) {
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gk20a_wait_until_counter_is_N(
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nvgpu_channel_wait_until_counter_is_N(
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ch, &ch->ref_count, 1, &ch->ref_count_dec_wq,
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__func__, "references");
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}
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@@ -333,7 +333,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force)
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/* wait until no more refs to the channel */
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if (!force) {
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gk20a_wait_until_counter_is_N(
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nvgpu_channel_wait_until_counter_is_N(
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ch, &ch->ref_count, 0, &ch->ref_count_dec_wq,
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__func__, "references");
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}
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@@ -899,7 +899,7 @@ void nvgpu_channel_free_priv_cmd_entry(struct nvgpu_channel *c,
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}
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}
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int nvgpu_gk20a_alloc_job(struct nvgpu_channel *c,
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int nvgpu_channel_alloc_job(struct nvgpu_channel *c,
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struct nvgpu_channel_job **job_out)
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{
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int err = 0;
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@@ -2094,7 +2094,7 @@ void nvgpu_channel_clean_up_jobs(struct nvgpu_channel *c,
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/*
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* ensure all pending writes complete before freeing up the job.
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* see corresponding nvgpu_smp_rmb in nvgpu_gk20a_alloc_job().
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* see corresponding nvgpu_smp_rmb in nvgpu_channel_alloc_job().
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*/
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nvgpu_smp_wmb();
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@@ -2152,9 +2152,9 @@ void nvgpu_channel_update(struct nvgpu_channel *c)
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*
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* Takes write access on g->deterministic_busy.
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*
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* Must be paired with gk20a_channel_deterministic_unidle().
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* Must be paired with nvgpu_channel_deterministic_unidle().
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*/
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void gk20a_channel_deterministic_idle(struct gk20a *g)
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void nvgpu_channel_deterministic_idle(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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u32 chid;
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@@ -2195,7 +2195,7 @@ void gk20a_channel_deterministic_idle(struct gk20a *g)
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*
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* This releases write access on g->deterministic_busy.
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*/
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void gk20a_channel_deterministic_unidle(struct gk20a *g)
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void nvgpu_channel_deterministic_unidle(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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u32 chid;
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@@ -525,7 +525,7 @@ static int nvgpu_submit_channel_gpfifo(struct nvgpu_channel *c,
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}
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if (need_job_tracking) {
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err = nvgpu_gk20a_alloc_job(c, &job);
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err = nvgpu_channel_alloc_job(c, &job);
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if (err != 0) {
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goto clean_up;
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}
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@@ -441,8 +441,8 @@ int nvgpu_channel_disable_tsg(struct gk20a *g, struct nvgpu_channel *ch);
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int nvgpu_channel_suspend_all_serviceable_ch(struct gk20a *g);
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void nvgpu_channel_resume_all_serviceable_ch(struct gk20a *g);
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void gk20a_channel_deterministic_idle(struct gk20a *g);
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void gk20a_channel_deterministic_unidle(struct gk20a *g);
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void nvgpu_channel_deterministic_idle(struct gk20a *g);
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void nvgpu_channel_deterministic_unidle(struct gk20a *g);
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int nvgpu_channel_worker_init(struct gk20a *g);
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void nvgpu_channel_worker_deinit(struct gk20a *g);
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@@ -483,10 +483,10 @@ bool nvgpu_channel_joblist_is_empty(struct nvgpu_channel *c);
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int nvgpu_channel_update_runlist(struct nvgpu_channel *c, bool add);
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void gk20a_wait_until_counter_is_N(
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void nvgpu_channel_wait_until_counter_is_N(
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struct nvgpu_channel *ch, nvgpu_atomic_t *counter, int wait_value,
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struct nvgpu_cond *c, const char *caller, const char *counter_name);
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int nvgpu_gk20a_alloc_job(struct nvgpu_channel *c,
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int nvgpu_channel_alloc_job(struct nvgpu_channel *c,
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struct nvgpu_channel_job **job_out);
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void nvgpu_channel_free_job(struct nvgpu_channel *c,
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struct nvgpu_channel_job *job);
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@@ -519,7 +519,7 @@ int gk20a_do_idle_impl(struct gk20a *g, bool force_reset)
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* Hold back deterministic submits and changes to deterministic
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* channels - this must be outside the power busy locks.
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*/
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gk20a_channel_deterministic_idle(g);
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nvgpu_channel_deterministic_idle(g);
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/* acquire busy lock to block other busy() calls */
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down_write(&l->busy_lock);
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@@ -626,7 +626,7 @@ fail_drop_usage_count:
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fail_timeout:
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nvgpu_mutex_release(&platform->railgate_lock);
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up_write(&l->busy_lock);
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gk20a_channel_deterministic_unidle(g);
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nvgpu_channel_deterministic_unidle(g);
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return -EBUSY;
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}
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@@ -676,7 +676,7 @@ int gk20a_do_unidle_impl(struct gk20a *g)
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nvgpu_mutex_release(&platform->railgate_lock);
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up_write(&l->busy_lock);
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gk20a_channel_deterministic_unidle(g);
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nvgpu_channel_deterministic_unidle(g);
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return 0;
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}
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