diff --git a/drivers/gpu/nvgpu/gv100/acr_gv100.h b/drivers/gpu/nvgpu/gv100/acr_gv100.h
index e5e7c454c..f77e62a3e 100644
--- a/drivers/gpu/nvgpu/gv100/acr_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/acr_gv100.h
@@ -20,10 +20,10 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_ACR_GV100_H_
-#define _NVGPU_ACR_GV100_H_
+#ifndef NVGPU_ACR_GV100_H
+#define NVGPU_ACR_GV100_H
 
 #define GV100_FECS_UCODE_SIG "gv100/fecs_sig.bin"
 #define GV100_GPCCS_UCODE_SIG "gv100/gpccs_sig.bin"
 
-#endif
+#endif /* NVGPU_ACR_GV100_H */
diff --git a/drivers/gpu/nvgpu/gv100/flcn_gv100.h b/drivers/gpu/nvgpu/gv100/flcn_gv100.h
index 9207519ae..f3116058e 100644
--- a/drivers/gpu/nvgpu/gv100/flcn_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/flcn_gv100.h
@@ -19,9 +19,9 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __FLCN_GV100_H__
-#define __FLCN_GV100_H__
+#ifndef NVGPU_FLCN_GV100_H
+#define NVGPU_FLCN_GV100_H
 
 int gv100_falcon_hal_sw_init(struct nvgpu_falcon *flcn);
 
-#endif /* __FLCN_GV100_H__ */
+#endif /* NVGPU_FLCN_GV100_H */
diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h
index 649a6b216..549912413 100644
--- a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h
@@ -19,8 +19,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __GR_CTX_GV100_H__
-#define __GR_CTX_GV100_H__
+#ifndef NVGPU_GR_CTX_GV100_H
+#define NVGPU_GR_CTX_GV100_H
 
 #include "gk20a/gr_ctx_gk20a.h"
 
@@ -30,4 +30,4 @@
 int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name);
 bool gr_gv100_is_firmware_defined(void);
 
-#endif /*__GR_CTX_GV100_H__*/
+#endif /* NVGPU_GR_CTX_GV100_H */
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h
index 6d6b4170e..aae87f09b 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_GR_GV100_H_
-#define _NVGPU_GR_GV100_H_
+#ifndef NVGPU_GR_GV100_H
+#define NVGPU_GR_GV100_H
 
 void gr_gv100_bundle_cb_defaults(struct gk20a *g);
 void gr_gv100_cb_size_default(struct gk20a *g);
@@ -48,4 +48,4 @@ void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr,
 	u32 *priv_addr_table, u32 *t);
 u32 gr_gv100_get_hw_accessor_stream_out_mode(void);
 void gr_gv100_init_hwpm_pmm_register(struct gk20a *g);
-#endif
+#endif /* NVGPU_GR_GV100_H */
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h
index 7564947e1..a4b295419 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h
@@ -22,11 +22,11 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVGPU_HAL_GV100_H
-#define _NVGPU_HAL_GV100_H
+#ifndef NVGPU_HAL_GV100_H
+#define NVGPU_HAL_GV100_H
 
 struct gk20a;
 
 int gv100_init_hal(struct gk20a *gops);
 
-#endif
+#endif /* NVGPU_HAL_GV100_H */
diff --git a/drivers/gpu/nvgpu/gv100/pmu_gv100.h b/drivers/gpu/nvgpu/gv100/pmu_gv100.h
index 4c8b35419..9e7672ebd 100644
--- a/drivers/gpu/nvgpu/gv100/pmu_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/pmu_gv100.h
@@ -22,12 +22,12 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef __PMU_GV100_H_
-#define __PMU_GV100_H_
+#ifndef NVGPU_PMU_GV100_H
+#define NVGPU_PMU_GV100_H
 
 struct gk20a;
 
 int gv100_pmu_init_acr(struct gk20a *g);
 int gv100_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
 
-#endif /*__PMU_GV100_H_*/
+#endif /* NVGPU_PMU_GV100_H */
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.h b/drivers/gpu/nvgpu/gv100/regops_gv100.h
index 4abfeaacd..14c39235b 100644
--- a/drivers/gpu/nvgpu/gv100/regops_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/regops_gv100.h
@@ -22,8 +22,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __REGOPS_GV100_H_
-#define __REGOPS_GV100_H_
+#ifndef NVGPU_REGOPS_GV100_H
+#define NVGPU_REGOPS_GV100_H
 
 const struct regop_offset_range *gv100_get_global_whitelist_ranges(void);
 u64 gv100_get_global_whitelist_ranges_count(void);
@@ -39,4 +39,4 @@ const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void);
 u64 gv100_get_qctl_whitelist_ranges_count(void);
 int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
-#endif /* __REGOPS_GV11B_H_ */
+#endif /* NVGPU_REGOPS_GV100_H */