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gpu: nvgpu: Code updates for MISRA violations
Regenerated the gating_reglist.c files for various chips after fixing the script for MISRA C-2012 violations Rule 15.5: Multiple points of exit detected Rule 15.6: "if" body without compound statement Rule 10.3: Implicit conversions of 64bit to 32bit int Rule 7.2: Const must be declared with "U" Rule 5.7: Tags with name xxx already declared Add preprocessor conditional gaurds in gating_reglist header files JIRA NVGPU-671 JIRA NVGPU-656 JIRA NVGPU-688 JIRA NVGPU-686 JIRA NVGPU-644 Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724444 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Vinod G
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0f81c5616b
35
drivers/gpu/nvgpu/common/clock_gating/gating_reglist.h
Normal file
35
drivers/gpu/nvgpu/common/clock_gating/gating_reglist.h
Normal file
@@ -0,0 +1,35 @@
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/*
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*
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* Copyright (c) 2018, NVIDIA Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef GATING_REGLIST_H
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#define GATING_REGLIST_H
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struct gating_desc {
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u32 addr;
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u32 prod;
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u32 disable;
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};
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#endif /* GATING_REGLIST_H */
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File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,5 @@
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/*
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* drivers/video/tegra/host/gm20b/gm20b_gating_reglist.h
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*
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* Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2014-2018, NVIDIA Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -20,11 +18,12 @@
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* This file is autogenerated. Do not edit.
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*/
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#include "gk20a/gk20a.h"
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#ifndef GM20B_GATING_REGLIST_H
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#define GM20B_GATING_REGLIST_H
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struct gk20a;
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void gm20b_slcg_bus_load_gating_prod(struct gk20a *g,
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bool prod);
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@@ -97,4 +96,4 @@ void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g,
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void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g,
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bool prod);
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#endif /* GM20B_GATING_REGLIST_H */
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -22,249 +22,241 @@
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* This file is autogenerated. Do not edit.
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*/
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#ifndef __gp106_gating_reglist_h__
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#define __gp106_gating_reglist_h__
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#include "gp106_gating_reglist.h"
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#include <nvgpu/types.h>
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#include <nvgpu/io.h>
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#include <nvgpu/enabled.h>
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struct gating_desc {
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u32 addr;
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u32 prod;
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u32 disable;
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};
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#include "gating_reglist.h"
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#include "gp106_gating_reglist.h"
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#define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc))
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/* slcg bus */
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static const struct gating_desc gp106_slcg_bus[] = {
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{.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
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{.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU},
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};
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/* slcg ce2 */
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static const struct gating_desc gp106_slcg_ce2[] = {
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{.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
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{.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU},
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};
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/* slcg chiplet */
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static const struct gating_desc gp106_slcg_chiplet[] = {
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{.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
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{.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U},
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{.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U},
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{.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U},
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{.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U},
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};
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/* slcg fb */
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static const struct gating_desc gp106_slcg_fb[] = {
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{.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU},
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{.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU},
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};
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/* slcg fifo */
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static const struct gating_desc gp106_slcg_fifo[] = {
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{.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x000026acU, .prod = 0x00000f40U, .disable = 0x0001fffeU},
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};
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/* slcg gr */
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static const struct gating_desc gp106_slcg_gr[] = {
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{.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe},
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{.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
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{.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
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{.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
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{.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
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{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
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{.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
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{.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
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{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
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{.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe},
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{.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
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{.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},
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{.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe},
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{.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
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{.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
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{.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
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{.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
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{.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
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{.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
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{.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
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{.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
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{.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
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{.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
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{.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
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{.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
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{.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
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{.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
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{.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
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{.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
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{.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
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{.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
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{.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
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{.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
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{.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
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{.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
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{.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
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{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
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{.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
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{.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
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{.addr = 0x004041f4U, .prod = 0x00000002U, .disable = 0x03fffffeU},
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{.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
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{.addr = 0x00409894U, .prod = 0x00000040U, .disable = 0x03fffffeU},
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{.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU},
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{.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU},
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{.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
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{.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
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{.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU},
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{.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU},
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{.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
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{.addr = 0x0041a894U, .prod = 0x00000040U, .disable = 0x03fffffeU},
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{.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU},
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{.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},
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{.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
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{.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x0000003eU},
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{.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
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{.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
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{.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
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{.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
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{.addr = 0x00418c74U, .prod = 0xffffffc0U, .disable = 0xfffffffeU},
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{.addr = 0x00418cf4U, .prod = 0xfffffffcU, .disable = 0xfffffffeU},
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{.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
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{.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
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{.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU},
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{.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU},
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{.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU},
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{.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x0000ffffU},
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{.addr = 0x00419a44U, .prod = 0x00000000U, .disable = 0x0000000eU},
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{.addr = 0x00419a4cU, .prod = 0x00000000U, .disable = 0x000001feU},
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{.addr = 0x00419a54U, .prod = 0x00000000U, .disable = 0x0000003eU},
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{.addr = 0x00419a5cU, .prod = 0x00000000U, .disable = 0x0000000eU},
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{.addr = 0x00419a64U, .prod = 0x00000000U, .disable = 0x000001feU},
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{.addr = 0x00419a6cU, .prod = 0x00000000U, .disable = 0x0000000eU},
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{.addr = 0x00419a74U, .prod = 0x00000000U, .disable = 0x0000000eU},
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{.addr = 0x00419a7cU, .prod = 0x00000000U, .disable = 0x0000003eU},
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{.addr = 0x00419a84U, .prod = 0x00000000U, .disable = 0x0000000eU},
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{.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
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{.addr = 0x00419cd8U, .prod = 0x00000000U, .disable = 0x001ffffeU},
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{.addr = 0x00419ce0U, .prod = 0x00000000U, .disable = 0x001ffffeU},
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{.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
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{.addr = 0x00419fd4U, .prod = 0x00000000U, .disable = 0x0003fffeU},
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{.addr = 0x00419fdcU, .prod = 0xffedff00U, .disable = 0xfffffffeU},
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{.addr = 0x00419fe4U, .prod = 0x00001b00U, .disable = 0x00001ffeU},
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{.addr = 0x00419ff4U, .prod = 0x00000000U, .disable = 0x00003ffeU},
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{.addr = 0x00419ffcU, .prod = 0x00000000U, .disable = 0x0001fffeU},
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{.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
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{.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
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{.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
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{.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
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{.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
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{.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
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{.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x0000ffffU},
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};
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/* slcg ltc */
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static const struct gating_desc gp106_slcg_ltc[] = {
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{.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
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{.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
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{.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
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};
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/* slcg perf */
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static const struct gating_desc gp106_slcg_perf[] = {
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{.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
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{.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
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{.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000},
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{.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
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{.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000},
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{.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
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{.addr = 0x001be018U, .prod = 0x000001ffU, .disable = 0x00000000U},
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{.addr = 0x001bc018U, .prod = 0x000001ffU, .disable = 0x00000000U},
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{.addr = 0x001b8018U, .prod = 0x000001ffU, .disable = 0x00000000U},
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{.addr = 0x001b4124U, .prod = 0x00000001U, .disable = 0x00000000U},
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};
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/* slcg PriRing */
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static const struct gating_desc gp106_slcg_priring[] = {
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{.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
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{.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U},
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};
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/* slcg pmu */
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static const struct gating_desc gp106_slcg_pmu[] = {
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{.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
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{.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe},
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{.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
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{.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
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{.addr = 0x0010aa74U, .prod = 0x00004000U, .disable = 0x00007ffeU},
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{.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU},
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};
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/* therm gr */
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static const struct gating_desc gp106_slcg_therm[] = {
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{.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
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{.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x0000000fU},
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};
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/* slcg Xbar */
|
||||
static const struct gating_desc gp106_slcg_xbar[] = {
|
||||
{.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe},
|
||||
{.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe},
|
||||
{.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe},
|
||||
{.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
|
||||
{.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
|
||||
{.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe},
|
||||
{.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
|
||||
{.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
|
||||
};
|
||||
|
||||
/* blcg bus */
|
||||
static const struct gating_desc gp106_blcg_bus[] = {
|
||||
{.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U},
|
||||
};
|
||||
|
||||
/* blcg ce */
|
||||
static const struct gating_desc gp106_blcg_ce[] = {
|
||||
{.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00104200U, .prod = 0x00008242U, .disable = 0x00000000U},
|
||||
};
|
||||
|
||||
/* blcg ctxsw prog */
|
||||
static const struct gating_desc gp106_blcg_ctxsw_prog[] = {
|
||||
};
|
||||
|
||||
/* blcg fb */
|
||||
static const struct gating_desc gp106_blcg_fb[] = {
|
||||
{.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
|
||||
{.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
|
||||
{.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
/* fix priv error */
|
||||
/*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/
|
||||
{.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U},
|
||||
};
|
||||
|
||||
/* blcg fifo */
|
||||
static const struct gating_desc gp106_blcg_fifo[] = {
|
||||
{.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x000026a4U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
};
|
||||
|
||||
/* blcg gr */
|
||||
static const struct gating_desc gp106_blcg_gr[] = {
|
||||
{.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
|
||||
{.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
|
||||
{.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
|
||||
{.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
|
||||
{.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
|
||||
{.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
|
||||
{.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
|
||||
{.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
|
||||
{.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
|
||||
{.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
|
||||
{.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
|
||||
{.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
|
||||
{.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
|
||||
{.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
|
||||
{.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
|
||||
{.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
|
||||
{.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
|
||||
{.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
|
||||
{.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
|
||||
{.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
|
||||
{.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
|
||||
{.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
|
||||
{.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U},
|
||||
{.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U},
|
||||
{.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
|
||||
{.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U},
|
||||
{.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
|
||||
{.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418e0cU, .prod = 0x00008444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U},
|
||||
{.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a40U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a48U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a50U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a58U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a60U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a68U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a70U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a78U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419868U, .prod = 0x00008242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419cd4U, .prod = 0x00000002U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419cdcU, .prod = 0x00000002U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419fd0U, .prod = 0x0000c044U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419fd8U, .prod = 0x0000c046U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419fe0U, .prod = 0x0000c044U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419fe8U, .prod = 0x0000c042U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419ff0U, .prod = 0x0000c045U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419ff8U, .prod = 0x00000002U, .disable = 0x00000000U},
|
||||
{.addr = 0x00419f90U, .prod = 0x00000002U, .disable = 0x00000000U},
|
||||
{.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U},
|
||||
{.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U},
|
||||
{.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
{.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U},
|
||||
};
|
||||
|
||||
/* blcg ltc */
|
||||
static const struct gating_desc gp106_blcg_ltc[] = {
|
||||
{.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
|
||||
{.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U},
|
||||
{.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U},
|
||||
{.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},
|
||||
{.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},
|
||||
};
|
||||
|
||||
/* blcg pmu */
|
||||
static const struct gating_desc gp106_blcg_pmu[] = {
|
||||
{.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
|
||||
{.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U},
|
||||
};
|
||||
|
||||
/* blcg Xbar */
|
||||
static const struct gating_desc gp106_blcg_xbar[] = {
|
||||
{.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000},
|
||||
{.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000},
|
||||
{.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000},
|
||||
{.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000},
|
||||
{.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U},
|
||||
{.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U},
|
||||
};
|
||||
|
||||
/* pg gr */
|
||||
@@ -276,18 +268,15 @@ void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_bus) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_bus[i].addr,
|
||||
gp106_slcg_bus[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_bus[i].addr,
|
||||
gp106_slcg_bus[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_bus[i].addr;
|
||||
u32 val = prod ? gp106_slcg_bus[i].prod :
|
||||
gp106_slcg_bus[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -295,18 +284,15 @@ void gp106_slcg_ce2_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_ce2) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_ce2[i].addr,
|
||||
gp106_slcg_ce2[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_ce2[i].addr,
|
||||
gp106_slcg_ce2[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_ce2[i].addr;
|
||||
u32 val = prod ? gp106_slcg_ce2[i].prod :
|
||||
gp106_slcg_ce2[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -314,42 +300,38 @@ void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_chiplet) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_chiplet[i].addr,
|
||||
gp106_slcg_chiplet[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_chiplet[i].addr,
|
||||
gp106_slcg_chiplet[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_chiplet[i].addr;
|
||||
u32 val = prod ? gp106_slcg_chiplet[i].prod :
|
||||
gp106_slcg_chiplet[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
}
|
||||
}
|
||||
|
||||
void gp106_slcg_fb_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_fb) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_fb[i].addr,
|
||||
gp106_slcg_fb[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_fb[i].addr,
|
||||
gp106_slcg_fb[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_fb[i].addr;
|
||||
u32 val = prod ? gp106_slcg_fb[i].prod :
|
||||
gp106_slcg_fb[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -357,18 +339,15 @@ void gp106_slcg_fifo_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_fifo) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_fifo[i].addr,
|
||||
gp106_slcg_fifo[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_fifo[i].addr,
|
||||
gp106_slcg_fifo[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_fifo[i].addr;
|
||||
u32 val = prod ? gp106_slcg_fifo[i].prod :
|
||||
gp106_slcg_fifo[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -376,18 +355,15 @@ void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_gr) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_gr[i].addr,
|
||||
gp106_slcg_gr[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_gr[i].addr,
|
||||
gp106_slcg_gr[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_gr[i].addr;
|
||||
u32 val = prod ? gp106_slcg_gr[i].prod :
|
||||
gp106_slcg_gr[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -395,18 +371,15 @@ void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
u32 size = (u32)(sizeof(gp106_slcg_ltc) / GATING_DESC_SIZE);
|
||||
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_ltc[i].addr,
|
||||
gp106_slcg_ltc[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_ltc[i].addr,
|
||||
gp106_slcg_ltc[i].disable);
|
||||
u32 reg = gp106_slcg_ltc[i].addr;
|
||||
u32 val = prod ? gp106_slcg_ltc[i].prod :
|
||||
gp106_slcg_ltc[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -414,18 +387,15 @@ void gp106_slcg_perf_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_perf) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_perf[i].addr,
|
||||
gp106_slcg_perf[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_perf[i].addr,
|
||||
gp106_slcg_perf[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_perf[i].addr;
|
||||
u32 val = prod ? gp106_slcg_perf[i].prod :
|
||||
gp106_slcg_perf[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -433,18 +403,15 @@ void gp106_slcg_priring_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_priring) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_priring[i].addr,
|
||||
gp106_slcg_priring[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_priring[i].addr,
|
||||
gp106_slcg_priring[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_priring[i].addr;
|
||||
u32 val = prod ? gp106_slcg_priring[i].prod :
|
||||
gp106_slcg_priring[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -452,18 +419,15 @@ void gp106_slcg_pmu_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_pmu) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_pmu[i].addr,
|
||||
gp106_slcg_pmu[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_pmu[i].addr,
|
||||
gp106_slcg_pmu[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_pmu[i].addr;
|
||||
u32 val = prod ? gp106_slcg_pmu[i].prod :
|
||||
gp106_slcg_pmu[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -471,18 +435,15 @@ void gp106_slcg_therm_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_therm) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_therm[i].addr,
|
||||
gp106_slcg_therm[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_therm[i].addr,
|
||||
gp106_slcg_therm[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_therm[i].addr;
|
||||
u32 val = prod ? gp106_slcg_therm[i].prod :
|
||||
gp106_slcg_therm[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -490,18 +451,15 @@ void gp106_slcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_slcg_xbar) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_slcg_xbar[i].addr,
|
||||
gp106_slcg_xbar[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_slcg_xbar[i].addr,
|
||||
gp106_slcg_xbar[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_slcg_xbar[i].addr;
|
||||
u32 val = prod ? gp106_slcg_xbar[i].prod :
|
||||
gp106_slcg_xbar[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -509,18 +467,15 @@ void gp106_blcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_blcg_bus) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_blcg_bus[i].addr,
|
||||
gp106_blcg_bus[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_blcg_bus[i].addr,
|
||||
gp106_blcg_bus[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_blcg_bus[i].addr;
|
||||
u32 val = prod ? gp106_blcg_bus[i].prod :
|
||||
gp106_blcg_bus[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -528,18 +483,31 @@ void gp106_blcg_ce_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_blcg_ce) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_blcg_ce[i].addr;
|
||||
u32 val = prod ? gp106_blcg_ce[i].prod :
|
||||
gp106_blcg_ce[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_blcg_ce[i].addr,
|
||||
gp106_blcg_ce[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_blcg_ce[i].addr,
|
||||
gp106_blcg_ce[i].disable);
|
||||
void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = (u32)(sizeof(gp106_blcg_ctxsw_prog) / GATING_DESC_SIZE);
|
||||
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_blcg_ctxsw_prog[i].addr;
|
||||
u32 val = prod ? gp106_blcg_ctxsw_prog[i].prod :
|
||||
gp106_blcg_ctxsw_prog[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -547,18 +515,15 @@ void gp106_blcg_fb_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_blcg_fb) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_blcg_fb[i].addr,
|
||||
gp106_blcg_fb[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_blcg_fb[i].addr,
|
||||
gp106_blcg_fb[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_blcg_fb[i].addr;
|
||||
u32 val = prod ? gp106_blcg_fb[i].prod :
|
||||
gp106_blcg_fb[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -566,18 +531,15 @@ void gp106_blcg_fifo_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
u32 size = (u32)(sizeof(gp106_blcg_fifo) / GATING_DESC_SIZE);
|
||||
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_blcg_fifo[i].addr,
|
||||
gp106_blcg_fifo[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_blcg_fifo[i].addr,
|
||||
gp106_blcg_fifo[i].disable);
|
||||
u32 reg = gp106_blcg_fifo[i].addr;
|
||||
u32 val = prod ? gp106_blcg_fifo[i].prod :
|
||||
gp106_blcg_fifo[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -585,18 +547,15 @@ void gp106_blcg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_blcg_gr) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_blcg_gr[i].addr,
|
||||
gp106_blcg_gr[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_blcg_gr[i].addr,
|
||||
gp106_blcg_gr[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_blcg_gr[i].addr;
|
||||
u32 val = prod ? gp106_blcg_gr[i].prod :
|
||||
gp106_blcg_gr[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -604,18 +563,15 @@ void gp106_blcg_ltc_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_blcg_ltc) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_blcg_ltc[i].addr,
|
||||
gp106_blcg_ltc[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_blcg_ltc[i].addr,
|
||||
gp106_blcg_ltc[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_blcg_ltc[i].addr;
|
||||
u32 val = prod ? gp106_blcg_ltc[i].prod :
|
||||
gp106_blcg_ltc[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -623,18 +579,15 @@ void gp106_blcg_pmu_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_blcg_pmu) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_blcg_pmu[i].addr,
|
||||
gp106_blcg_pmu[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_blcg_pmu[i].addr,
|
||||
gp106_blcg_pmu[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_blcg_pmu[i].addr;
|
||||
u32 val = prod ? gp106_blcg_pmu[i].prod :
|
||||
gp106_blcg_pmu[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -642,18 +595,15 @@ void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_blcg_xbar) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_blcg_xbar[i].addr,
|
||||
gp106_blcg_xbar[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_blcg_xbar[i].addr,
|
||||
gp106_blcg_xbar[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_blcg_xbar[i].addr;
|
||||
u32 val = prod ? gp106_blcg_xbar[i].prod :
|
||||
gp106_blcg_xbar[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -661,19 +611,14 @@ void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod)
|
||||
{
|
||||
u32 i;
|
||||
u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc);
|
||||
u32 size = (u32)(sizeof(gp106_pg_gr) / GATING_DESC_SIZE);
|
||||
|
||||
if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
|
||||
return;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (prod)
|
||||
gk20a_writel(g, gp106_pg_gr[i].addr,
|
||||
gp106_pg_gr[i].prod);
|
||||
else
|
||||
gk20a_writel(g, gp106_pg_gr[i].addr,
|
||||
gp106_pg_gr[i].disable);
|
||||
if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
|
||||
for (i = 0; i < size; i++) {
|
||||
u32 reg = gp106_pg_gr[i].addr;
|
||||
u32 val = prod ? gp106_pg_gr[i].prod :
|
||||
gp106_pg_gr[i].disable;
|
||||
gk20a_writel(g, reg, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __gp106_gating_reglist_h__ */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2018, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -20,7 +20,10 @@
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "gk20a/gk20a.h"
|
||||
#ifndef GP106_GATING_REGLIST_H
|
||||
#define GP106_GATING_REGLIST_H
|
||||
|
||||
struct gk20a;
|
||||
|
||||
void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
@@ -90,4 +93,4 @@ void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
|
||||
void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
#endif /* GP106_GATING_REGLIST_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2018, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -20,7 +20,10 @@
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "gk20a/gk20a.h"
|
||||
#ifndef GP10B_GATING_REGLIST_H
|
||||
#define GP10B_GATING_REGLIST_H
|
||||
|
||||
struct gk20a;
|
||||
|
||||
void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
@@ -96,4 +99,4 @@ void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
|
||||
void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
#endif /* GP10B_GATING_REGLIST_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -20,7 +20,10 @@
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "gk20a/gk20a.h"
|
||||
#ifndef GV100_GATING_REGLIST_H
|
||||
#define GV100_GATING_REGLIST_H
|
||||
|
||||
struct gk20a;
|
||||
|
||||
void gv100_slcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
@@ -96,4 +99,4 @@ void gv100_blcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
|
||||
void gr_gv100_pg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
#endif /* GV100_GATING_REGLIST_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2016, NVIDIA Corporation. All rights reserved.
|
||||
* Copyright (c) 2016-2018, NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -20,7 +20,10 @@
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "gk20a/gk20a.h"
|
||||
#ifndef GV11B_GATING_REGLIST_H
|
||||
#define GV11B_GATING_REGLIST_H
|
||||
|
||||
struct gk20a;
|
||||
|
||||
void gv11b_slcg_bus_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
@@ -96,4 +99,4 @@ void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g,
|
||||
|
||||
void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g,
|
||||
bool prod);
|
||||
|
||||
#endif /* GV11B_GATING_REGLIST_H */
|
||||
|
||||
Reference in New Issue
Block a user