From 0f952a1a8525f01f864fd8a10f483be3a4707ad2 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Thu, 29 Nov 2018 14:24:37 +0530 Subject: [PATCH] gpu: nvgpu: use FALCON_MAILBOX_0 macro One of the mailbox 0 read and write hardcoded mailbox number. Use the macro instead. JIRA NVGPU-1459 Change-Id: Ic350c91c2100d09187c69724945dae920c9712c5 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/1961635 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fb/fb_gv100.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c index 91ae0850b..b98aad8fc 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c @@ -210,7 +210,8 @@ int gv100_fb_memory_unlock(struct gk20a *g) /* Write non-zero value to mailbox register which is updated by * mem_unlock bin to denote its return status. */ - nvgpu_falcon_mailbox_write(&g->nvdec_flcn, 0, 0xdeadbeef); + nvgpu_falcon_mailbox_write(&g->nvdec_flcn, + FALCON_MAILBOX_0, 0xdeadbeef); /* set BOOTVEC to start of non-secure code */ nvgpu_falcon_bootstrap(&g->nvdec_flcn, 0); @@ -219,7 +220,7 @@ int gv100_fb_memory_unlock(struct gk20a *g) nvgpu_falcon_wait_for_halt(&g->nvdec_flcn, MEM_UNLOCK_TIMEOUT); /* check mem unlock status */ - val = nvgpu_falcon_mailbox_read(&g->nvdec_flcn, 0); + val = nvgpu_falcon_mailbox_read(&g->nvdec_flcn, FALCON_MAILBOX_0); if (val != 0U) { nvgpu_err(g, "memory unlock failed, err %x", val); nvgpu_falcon_dump_stats(&g->nvdec_flcn);