diff --git a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export
index 4f0c80f97..160a9b0d9 100644
--- a/drivers/gpu/nvgpu/libnvgpu-drv_safe.export
+++ b/drivers/gpu/nvgpu/libnvgpu-drv_safe.export
@@ -130,7 +130,6 @@ nvgpu_gr_remove_support
 nvgpu_gr_prepare_sw
 nvgpu_gr_enable_hw
 nvgpu_gr_suspend
-nvgpu_gr_falcon_get_fecs_mutex
 nvgpu_gr_falcon_get_fecs_ucode_segments
 nvgpu_gr_falcon_get_gpccs_ucode_segments
 nvgpu_gr_falcon_get_surface_desc_cpu_va
diff --git a/userspace/units/gr/falcon/nvgpu-gr-falcon.c b/userspace/units/gr/falcon/nvgpu-gr-falcon.c
index ce84791e8..6a758dc46 100644
--- a/userspace/units/gr/falcon/nvgpu-gr-falcon.c
+++ b/userspace/units/gr/falcon/nvgpu-gr-falcon.c
@@ -151,19 +151,21 @@ static int test_gr_falcon_nonsecure_gpccs_recovery_ctxsw(struct unit_module *m,
 static int test_gr_falcon_query_test(struct unit_module *m,
 				struct gk20a *g, void *args)
 {
-
+#ifdef CONFIG_NVGPU_ENGINE_RESET
 	struct nvgpu_mutex *fecs_mutex =
 		nvgpu_gr_falcon_get_fecs_mutex(unit_gr_falcon);
+#endif
 	struct nvgpu_ctxsw_ucode_segments *fecs =
 		nvgpu_gr_falcon_get_fecs_ucode_segments(unit_gr_falcon);
 	struct nvgpu_ctxsw_ucode_segments *gpccs =
 		nvgpu_gr_falcon_get_gpccs_ucode_segments(unit_gr_falcon);
 	void *cpu_va = nvgpu_gr_falcon_get_surface_desc_cpu_va(unit_gr_falcon);
 
+#ifdef CONFIG_NVGPU_ENGINE_RESET
 	if (fecs_mutex == NULL) {
 		unit_return_fail(m, "nvgpu_gr_falcon_get_fecs_mutex failed\n");
 	}
-
+#endif
 	if (fecs == NULL) {
 		unit_return_fail(m,
 			"nvgpu_gr_falcon_get_fecs_ucode_segments failed\n");
diff --git a/userspace/units/gr/intr/nvgpu-gr-intr.c b/userspace/units/gr/intr/nvgpu-gr-intr.c
index 9f8d1be84..f871a7cbf 100644
--- a/userspace/units/gr/intr/nvgpu-gr-intr.c
+++ b/userspace/units/gr/intr/nvgpu-gr-intr.c
@@ -57,12 +57,14 @@ struct test_gr_intr_sw_mthd_exceptions {
 	int data[2];
 };
 
+#ifdef CONFIG_NVGPU_RECOVERY
 static void gr_test_intr_fifo_recover(struct gk20a *g, u32 bitmask, u32 id,
 		unsigned int id_type, unsigned int rc_type,
 		struct mmu_fault_info *mmufault)
 {
 	/* Remove once recovery support get disable for safety */
 }
+#endif
 
 static int test_gr_intr_setup(struct unit_module *m,
 		struct gk20a *g, void *args)
@@ -345,7 +347,9 @@ static int test_gr_intr_without_channel(struct unit_module *m,
 
 	g->ops.gr.intr.log_mme_exception = gr_test_intr_log_mme_exception;
 	g->ops.gr.intr.handle_tex_exception = gr_test_intr_tex_exception;
+#ifdef CONFIG_NVGPU_RECOVERY
 	g->ops.fifo.recover = gr_test_intr_fifo_recover;
+#endif
 
 	/* Set trapped address datahigh bit */
 	nvgpu_posix_io_writel_reg_space(g, gr_trapped_addr_r(),