diff --git a/drivers/gpu/nvgpu/common/acr/acr.c b/drivers/gpu/nvgpu/common/acr/acr.c index 464781670..2b224ab02 100644 --- a/drivers/gpu/nvgpu/common/acr/acr.c +++ b/drivers/gpu/nvgpu/common/acr/acr.c @@ -22,9 +22,10 @@ #include #include -#include +#include #include +#include "acr_priv.h" #include "acr_gm20b.h" #include "acr_gp10b.h" #include "acr_gv11b.h" @@ -34,6 +35,7 @@ /* Both size and address of WPR need to be 128K-aligned */ #define DGPU_WPR_SIZE 0x200000U +/* ACR common API's used within ACR unit */ int nvgpu_acr_alloc_blob_space_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem) { @@ -51,14 +53,14 @@ int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size, return 0; } - g->acr.get_wpr_info(g, &wpr_inf); + g->acr->get_wpr_info(g, &wpr_inf); /* * Even though this mem_desc wouldn't be used, the wpr region needs to * be reserved in the allocator. */ err = nvgpu_dma_alloc_vid_at(g, wpr_inf.size, - &g->acr.wpr_dummy, wpr_inf.wpr_base); + &g->acr->wpr_dummy, wpr_inf.wpr_base); if (err != 0) { return err; } @@ -79,58 +81,127 @@ void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf) inf->size = DGPU_WPR_SIZE; } -int nvgpu_acr_construct_execute(struct gk20a *g){ +/* ACR public API's */ +bool nvgpu_acr_is_lsf_lazy_bootstrap(struct gk20a *g, struct nvgpu_acr *acr, + u32 falcon_id) +{ + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL) || acr == NULL) { + return false; + } + + return acr->lsf[falcon_id].is_lazy_bootstrap; +} + +int nvgpu_acr_alloc_blob_prerequisite(struct gk20a *g, struct nvgpu_acr *acr, + size_t size) +{ + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + return 0; + } + + if (acr == NULL) { + return -EINVAL; + } + + return acr->alloc_blob_space(g, size, &acr->ucode_blob); +} + +/* ACR blob construct & bootstrap */ +int nvgpu_acr_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr) +{ + int err = 0; + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + return 0; + } + + if (acr == NULL) { + return -EINVAL; + } + + err = acr->bootstrap_hs_acr(g, acr, &acr->acr); + if (err != 0) { + nvgpu_err(g, "ACR bootstrap failed"); + } + + return err; +} + +int nvgpu_acr_construct_execute(struct gk20a *g, struct nvgpu_acr *acr) +{ + int err = 0; + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + return 0; + } + + if (acr == NULL) { + return -EINVAL; + } + + err = acr->prepare_ucode_blob(g); + if (err != 0) { + nvgpu_err(g, "ACR ucode blob prepare failed"); + goto done; + } + + err = nvgpu_acr_bootstrap_hs_acr(g, acr); + +done: + return err; +} + +/* ACR init */ +int nvgpu_acr_init(struct gk20a *g, struct nvgpu_acr **acr) +{ + u32 ver = g->params.gpu_arch + g->params.gpu_impl; int err = 0; if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { goto done; } - err = g->acr.prepare_ucode_blob(g); - if (err != 0) { - nvgpu_err(g, "ACR ucode blob prepare failed"); + if (*acr != NULL) { + /* + * Recovery/unrailgate case, we do not need to do ACR init as ACR is + * set during cold boot & doesn't execute ACR clean up as part off + * sequence, so reuse to perform faster boot. + */ + return err; + } + + *acr = (struct nvgpu_acr *) nvgpu_kzalloc(g, sizeof(struct nvgpu_acr)); + if (g->acr == NULL) { + err = -ENOMEM; goto done; } - err = g->acr.bootstrap_hs_acr(g, &g->acr, &g->acr.acr); - if (err != 0) { - nvgpu_err(g, "ACR bootstrap failed"); - goto done; + switch (ver) { + case GK20A_GPUID_GM20B: + case GK20A_GPUID_GM20B_B: + nvgpu_gm20b_acr_sw_init(g, *acr); + break; + case NVGPU_GPUID_GP10B: + nvgpu_gp10b_acr_sw_init(g, *acr); + break; + case NVGPU_GPUID_GV11B: + nvgpu_gv11b_acr_sw_init(g, *acr); + break; + case NVGPU_GPUID_GV100: + nvgpu_gv100_acr_sw_init(g, *acr); + break; + case NVGPU_GPUID_TU104: + nvgpu_tu104_acr_sw_init(g, *acr); + break; + default: + nvgpu_kfree(g, *acr); + err = -EINVAL; + nvgpu_err(g, "no support for GPUID %x", ver); + break; } done: return err; } -void nvgpu_acr_init(struct gk20a *g) -{ - u32 ver = g->params.gpu_arch + g->params.gpu_impl; - - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - return; - } - - switch (ver) { - case GK20A_GPUID_GM20B: - case GK20A_GPUID_GM20B_B: - nvgpu_gm20b_acr_sw_init(g, &g->acr); - break; - case NVGPU_GPUID_GP10B: - nvgpu_gp10b_acr_sw_init(g, &g->acr); - break; - case NVGPU_GPUID_GV11B: - nvgpu_gv11b_acr_sw_init(g, &g->acr); - break; - case NVGPU_GPUID_GV100: - nvgpu_gv100_acr_sw_init(g, &g->acr); - break; - case NVGPU_GPUID_TU104: - nvgpu_tu104_acr_sw_init(g, &g->acr); - break; - default: - nvgpu_err(g, "no support for GPUID %x", ver); - break; - } -} - diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c index f34f6d138..bac460216 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c @@ -20,15 +20,16 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include #include #include -#include #include #include #include +#include "acr_blob_construct_v0.h" +#include "acr_priv.h" + int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img) { struct nvgpu_pmu *pmu = &g->pmu; @@ -310,7 +311,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, pnode->lsb_header.flags = data; } - if (g->acr.lsf[falcon_id].is_priv_load) { + if (g->acr->lsf[falcon_id].is_priv_load) { pnode->lsb_header.flags |= NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE; } @@ -335,11 +336,11 @@ static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr *plsfm, /* Fill in static WPR header info*/ pnode->wpr_header.falcon_id = falcon_id; - pnode->wpr_header.bootstrap_owner = g->acr.bootstrap_owner; + pnode->wpr_header.bootstrap_owner = g->acr->bootstrap_owner; pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY; pnode->wpr_header.lazy_bootstrap = - (u32)g->acr.lsf[falcon_id].is_lazy_bootstrap; + (u32)g->acr->lsf[falcon_id].is_lazy_bootstrap; /* Fill in static LSB header info elsewhere */ lsfm_fill_static_lsb_hdr_info(g, falcon_id, pnode); @@ -353,7 +354,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g, struct ls_flcn_mgr *plsfm) { struct flcn_ucode_img ucode_img; - struct nvgpu_acr *acr = &g->acr; + struct nvgpu_acr *acr = g->acr; u32 falcon_id; u32 i; int err = 0; @@ -518,7 +519,7 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, * physical addresses of each respective segment. */ addr_base = p_lsfm->lsb_header.ucode_off; - g->acr.get_wpr_info(g, &wpr_inf); + g->acr->get_wpr_info(g, &wpr_inf); addr_base += wpr_inf.wpr_base; nvgpu_acr_dbg(g, "pmu loader cfg u32 addrbase %x\n", (u32)addr_base); /*From linux*/ @@ -539,7 +540,7 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, nvgpu_acr_dbg(g, "bl start off %d\n", desc->bootloader_start_offset); /* Populate the loader_config state*/ - ldr_cfg->dma_idx = g->acr.lsf[FALCON_ID_PMU].falcon_dma_idx; + ldr_cfg->dma_idx = g->acr->lsf[FALCON_ID_PMU].falcon_dma_idx; ldr_cfg->code_dma_base = addr_code; ldr_cfg->code_dma_base1 = 0x0; ldr_cfg->code_size_total = desc->app_size; @@ -591,7 +592,7 @@ static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, * physical addresses of each respective segment. */ addr_base = p_lsfm->lsb_header.ucode_off; - g->acr.get_wpr_info(g, &wpr_inf); + g->acr->get_wpr_info(g, &wpr_inf); addr_base += wpr_inf.wpr_base; nvgpu_acr_dbg(g, "gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, @@ -613,7 +614,7 @@ static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, /* Populate the LOADER_CONFIG state */ (void) memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc)); - ldr_cfg->ctx_dma = g->acr.lsf[falconid].falcon_dma_idx; + ldr_cfg->ctx_dma = g->acr->lsf[falconid].falcon_dma_idx; ldr_cfg->code_dma_base = addr_code; ldr_cfg->non_sec_code_size = desc->app_resident_code_size; ldr_cfg->data_dma_base = addr_data; @@ -787,7 +788,7 @@ int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g) struct ls_flcn_mgr lsfm_l, *plsfm; struct wpr_carveout_info wpr_inf; - if (g->acr.ucode_blob.cpu_va != NULL) { + if (g->acr->ucode_blob.cpu_va != NULL) { /* Recovery case, we do not need to form non WPR blob */ return err; } @@ -797,7 +798,7 @@ int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g) g->ops.fb.vpr_info_fetch(g); gr_gk20a_init_ctxsw_ucode(g); - g->acr.get_wpr_info(g, &wpr_inf); + g->acr->get_wpr_info(g, &wpr_inf); nvgpu_acr_dbg(g, "wpr carveout base:%llx\n", wpr_inf.wpr_base); nvgpu_acr_dbg(g, "wpr carveout size :%llx\n", wpr_inf.size); @@ -809,7 +810,7 @@ int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g) } if ((plsfm->managed_flcn_cnt != 0U) && - (g->acr.ucode_blob.cpu_va == NULL)) { + (g->acr->ucode_blob.cpu_va == NULL)) { /* Generate WPR requirements */ err = lsf_gen_wpr_requirements(g, plsfm); if (err != 0) { @@ -817,15 +818,15 @@ int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g) } /* Alloc memory to hold ucode blob contents */ - err = g->acr.alloc_blob_space(g, plsfm->wpr_size - , &g->acr.ucode_blob); + err = g->acr->alloc_blob_space(g, plsfm->wpr_size + , &g->acr->ucode_blob); if (err != 0) { goto free_sgt; } nvgpu_acr_dbg(g, "managed LS falcon %d, WPR size %d bytes.\n", plsfm->managed_flcn_cnt, plsfm->wpr_size); - lsfm_init_wpr_contents(g, plsfm, &g->acr.ucode_blob); + lsfm_init_wpr_contents(g, plsfm, &g->acr->ucode_blob); } else { nvgpu_acr_dbg(g, "LSFM is managing no falcons.\n"); } diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h new file mode 100644 index 000000000..e533e0b6a --- /dev/null +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef ACR_BLOB_CONSTRUCT_V0_H +#define ACR_BLOB_CONSTRUCT_V0_H + +#include + +/* + * Light Secure WPR Content Alignments + */ +#define LSF_WPR_HEADER_ALIGNMENT (256U) +#define LSF_SUB_WPR_HEADER_ALIGNMENT (256U) +#define LSF_LSB_HEADER_ALIGNMENT (256U) +#define LSF_BL_DATA_ALIGNMENT (256U) +#define LSF_BL_DATA_SIZE_ALIGNMENT (256U) +#define LSF_BL_CODE_SIZE_ALIGNMENT (256U) +#define LSF_DATA_SIZE_ALIGNMENT (256U) +#define LSF_CODE_SIZE_ALIGNMENT (256U) + +#define LSF_UCODE_DATA_ALIGNMENT 4096U + + +/* Defined for 1MB alignment */ +#define SHIFT_1MB (20U) +#define SHIFT_4KB (12U) + +/* + * Maximum WPR Header size + */ +#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \ + (ALIGN_UP(((u32)sizeof(struct lsf_wpr_header_v1) * FALCON_ID_END), \ + LSF_WPR_HEADER_ALIGNMENT)) + +/*Light Secure Bootstrap header related defines*/ +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0U +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE BIT32(0) +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2) +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3) +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U + +/* + * Image Status Defines + */ +#define LSF_IMAGE_STATUS_NONE (0U) +#define LSF_IMAGE_STATUS_COPY (1U) +#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U) +#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U) +#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U) +#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U) +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U) + +/* + * Light Secure WPR Header + * Defines state allowing Light Secure Falcon bootstrapping. + */ +struct lsf_wpr_header { + u32 falcon_id; + u32 lsb_offset; + u32 bootstrap_owner; + u32 lazy_bootstrap; + u32 status; +}; + +/* + * Light Secure Falcon Ucode Description Defines + * This structure is prelim and may change as the ucode signing flow evolves. + */ +struct lsf_ucode_desc { + u8 prd_keys[2][16]; + u8 dbg_keys[2][16]; + u32 b_prd_present; + u32 b_dbg_present; + u32 falcon_id; +}; + +/* + * Light Secure Bootstrap Header + * Defines state allowing Light Secure Falcon bootstrapping. + */ +struct lsf_lsb_header { + struct lsf_ucode_desc signature; + u32 ucode_off; + u32 ucode_size; + u32 data_size; + u32 bl_code_size; + u32 bl_imem_off; + u32 bl_data_off; + u32 bl_data_size; + u32 app_code_off; + u32 app_code_size; + u32 app_data_off; + u32 app_data_size; + u32 flags; +}; + +/* Falcon BL interfaces */ +/* + * Structure used by the boot-loader to load the rest of the code. This has + * to be filled by NVGPU and copied into DMEM at offset provided in the + * hsflcn_bl_desc.bl_desc_dmem_load_off. + */ +struct flcn_bl_dmem_desc { + u32 reserved[4]; /*Should be the first element..*/ + u32 signature[4]; /*Should be the first element..*/ + u32 ctx_dma; + u32 code_dma_base; + u32 non_sec_code_off; + u32 non_sec_code_size; + u32 sec_code_off; + u32 sec_code_size; + u32 code_entry_point; + u32 data_dma_base; + u32 data_size; + u32 code_dma_base1; + u32 data_dma_base1; +}; + +/* + * Legacy structure used by the current PMU/DPU bootloader. + */ +struct loader_config { + u32 dma_idx; + u32 code_dma_base; /* upper 32-bits of 40-bit dma address */ + u32 code_size_total; + u32 code_size_to_load; + u32 code_entry_point; + u32 data_dma_base; /* upper 32-bits of 40-bit dma address */ + u32 data_size; /* initialized data of the application */ + u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */ + u32 argc; + u32 argv; + u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */ + u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */ + u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */ +}; + +/* + * Union of all supported structures used by bootloaders. + */ +union flcn_bl_generic_desc { + struct flcn_bl_dmem_desc bl_dmem_desc; + struct loader_config loader_cfg; +}; + +struct flcn_ucode_img { + u32 *header; /* only some falcons have header */ + u32 *data; + struct pmu_ucode_desc *desc; /* only some falcons have descriptor */ + u32 data_size; + void *fw_ver; /* CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct */ + u8 load_entire_os_data; /* load the whole osData section at boot time.*/ + /* NULL if not a light secure falcon. */ + struct lsf_ucode_desc *lsf_desc; + /* True if there a resources to freed by the client. */ + u8 free_res_allocs; + u32 flcn_inst; +}; + +/* + * LSFM Managed Ucode Image + * next : Next image the list, NULL if last. + * wpr_header : WPR header for this ucode image + * lsb_header : LSB header for this ucode image + * bl_gen_desc : Bootloader generic desc structure for this ucode image + * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image + * full_ucode_size : Surface size required for final ucode image + * ucode_img : Ucode image info + */ +struct lsfm_managed_ucode_img { + struct lsfm_managed_ucode_img *next; + struct lsf_wpr_header wpr_header; + struct lsf_lsb_header lsb_header; + union flcn_bl_generic_desc bl_gen_desc; + u32 bl_gen_desc_size; + u32 full_ucode_size; + struct flcn_ucode_img ucode_img; +}; + +/* + * Defines the structure used to contain all generic information related to + * the LSFM. + * + * Contains the Light Secure Falcon Manager (LSFM) feature related data. + */ +struct ls_flcn_mgr { + u16 managed_flcn_cnt; + u32 wpr_size; + struct lsfm_managed_ucode_img *ucode_img_list; +}; + +int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img); +int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img); +int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img); + +int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g); + +#endif /* ACR_BLOB_CONSTRUCT_V0_H */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c index 8c2951a78..4e6183fc5 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c @@ -20,17 +20,14 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include #include -#include #include #include #include -#include "acr_gm20b.h" -#include "acr_gv100.h" -#include "acr_tu104.h" +#include "acr_blob_construct_v1.h" +#include "acr_priv.h" static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value) { @@ -57,7 +54,7 @@ int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) lsf_desc->falcon_id = FALCON_ID_PMU; - p_img->desc = (struct pmu_ucode_desc_v1 *)(void *)pmu->fw_desc->data; + p_img->desc = (struct ls_falcon_ucode_desc *)(void *)pmu->fw_desc->data; p_img->data = (u32 *)(void *)pmu->fw_image->data; p_img->data_size = p_img->desc->app_start_offset + p_img->desc->app_size; p_img->fw_ver = NULL; @@ -107,7 +104,7 @@ int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) lsf_desc->falcon_id = FALCON_ID_FECS; - p_img->desc = nvgpu_kzalloc(g, sizeof(struct pmu_ucode_desc_v1)); + p_img->desc = nvgpu_kzalloc(g, sizeof(struct ls_falcon_ucode_desc)); if (p_img->desc == NULL) { err = -ENOMEM; goto free_lsf_desc; @@ -201,7 +198,7 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) min_t(size_t, sizeof(*lsf_desc), gpccs_sig->size)); lsf_desc->falcon_id = FALCON_ID_GPCCS; - p_img->desc = nvgpu_kzalloc(g, sizeof(struct pmu_ucode_desc_v1)); + p_img->desc = nvgpu_kzalloc(g, sizeof(struct ls_falcon_ucode_desc)); if (p_img->desc == NULL) { err = -ENOMEM; goto free_lsf_desc; @@ -255,7 +252,7 @@ rel_sig: int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) { struct nvgpu_firmware *sec2_fw, *sec2_desc, *sec2_sig; - struct pmu_ucode_desc_v1 *desc; + struct ls_falcon_ucode_desc *desc; struct lsf_ucode_desc_v1 *lsf_desc; struct flcn_ucode_img_v1 *p_img = (struct flcn_ucode_img_v1 *)lsf_ucode_img; @@ -281,7 +278,7 @@ int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img) goto release_img_fw; } - desc = (struct pmu_ucode_desc_v1 *)sec2_desc->data; + desc = (struct ls_falcon_ucode_desc *)sec2_desc->data; sec2_sig = nvgpu_request_firmware(g, LSF_SEC2_UCODE_SIG_BIN, NVGPU_REQUEST_FIRMWARE_NO_SOC); @@ -424,7 +421,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, pnode->lsb_header.flags = data; } - if (g->acr.lsf[falcon_id].is_priv_load) { + if (g->acr->lsf[falcon_id].is_priv_load) { pnode->lsb_header.flags |= NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE; } @@ -448,11 +445,11 @@ static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, /* Fill in static WPR header info*/ pnode->wpr_header.falcon_id = falcon_id; - pnode->wpr_header.bootstrap_owner = g->acr.bootstrap_owner; + pnode->wpr_header.bootstrap_owner = g->acr->bootstrap_owner; pnode->wpr_header.status = LSF_IMAGE_STATUS_COPY; pnode->wpr_header.lazy_bootstrap = - (u32)g->acr.lsf[falcon_id].is_lazy_bootstrap; + (u32)g->acr->lsf[falcon_id].is_lazy_bootstrap; /* Fill in static LSB header info elsewhere */ lsfm_fill_static_lsb_hdr_info(g, falcon_id, pnode); @@ -468,7 +465,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm) { struct flcn_ucode_img_v1 ucode_img; - struct nvgpu_acr *acr = &g->acr; + struct nvgpu_acr *acr = g->acr; u32 falcon_id; u32 i; int err = 0; @@ -684,9 +681,9 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g, (struct lsfm_managed_ucode_img_v2 *)lsfm; struct flcn_ucode_img_v1 *p_img = &(p_lsfm->ucode_img); struct flcn_bl_dmem_desc_v1 *ldr_cfg = - &(p_lsfm->bl_gen_desc.bl_dmem_desc_v1); + &(p_lsfm->bl_gen_desc); u64 addr_base; - struct pmu_ucode_desc_v1 *desc; + struct ls_falcon_ucode_desc *desc; u64 addr_code, addr_data; if (p_img->desc == NULL) { @@ -707,7 +704,7 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g, * physical addresses of each respective segment. */ addr_base = p_lsfm->lsb_header.ucode_off; - g->acr.get_wpr_info(g, &wpr_inf); + g->acr->get_wpr_info(g, &wpr_inf); addr_base += wpr_inf.wpr_base; nvgpu_acr_dbg(g, "falcon ID %x", p_lsfm->wpr_header.falcon_id); @@ -723,7 +720,7 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g, (void) memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc_v1)); - ldr_cfg->ctx_dma = g->acr.lsf[falconid].falcon_dma_idx; + ldr_cfg->ctx_dma = g->acr->lsf[falconid].falcon_dma_idx; flcn64_set_dma(&ldr_cfg->code_dma_base, addr_code); ldr_cfg->non_sec_code_off = desc->app_resident_code_offset; ldr_cfg->non_sec_code_size = desc->app_resident_code_size; @@ -733,8 +730,8 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g, /* Update the argc/argv members*/ ldr_cfg->argc = 1; - if (g->acr.lsf[falconid].get_cmd_line_args_offset != NULL) { - g->acr.lsf[falconid].get_cmd_line_args_offset(g, + if (g->acr->lsf[falconid].get_cmd_line_args_offset != NULL) { + g->acr->lsf[falconid].get_cmd_line_args_offset(g, &ldr_cfg->argv); } @@ -932,7 +929,7 @@ int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g) struct wpr_carveout_info wpr_inf; /* Recovery case, we do not need to form non WPR blob of ucodes */ - if (g->acr.ucode_blob.cpu_va != NULL) { + if (g->acr->ucode_blob.cpu_va != NULL) { return err; } @@ -940,7 +937,7 @@ int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g) (void) memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1)); gr_gk20a_init_ctxsw_ucode(g); - g->acr.get_wpr_info(g, &wpr_inf); + g->acr->get_wpr_info(g, &wpr_inf); nvgpu_acr_dbg(g, "wpr carveout base:%llx\n", (wpr_inf.wpr_base)); nvgpu_acr_dbg(g, "wpr carveout size :%x\n", (u32)wpr_inf.size); @@ -959,7 +956,7 @@ int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g) } if ((plsfm->managed_flcn_cnt != 0U) && - (g->acr.ucode_blob.cpu_va == NULL)) { + (g->acr->ucode_blob.cpu_va == NULL)) { /* Generate WPR requirements */ err = lsf_gen_wpr_requirements(g, plsfm); if (err != 0) { @@ -967,8 +964,8 @@ int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g) } /* Alloc memory to hold ucode blob contents */ - err = g->acr.alloc_blob_space(g, plsfm->wpr_size - ,&g->acr.ucode_blob); + err = g->acr->alloc_blob_space(g, plsfm->wpr_size + ,&g->acr->ucode_blob); if (err != 0) { goto exit_err; } @@ -976,7 +973,7 @@ int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g) nvgpu_acr_dbg(g, "managed LS falcon %d, WPR size %d bytes.\n", plsfm->managed_flcn_cnt, plsfm->wpr_size); - lsfm_init_wpr_contents(g, plsfm, &g->acr.ucode_blob); + lsfm_init_wpr_contents(g, plsfm, &g->acr->ucode_blob); } else { nvgpu_acr_dbg(g, "LSFM is managing no falcons.\n"); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h similarity index 52% rename from drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h rename to drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h index 606522489..96e9e2881 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h +++ b/drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,170 +19,12 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#ifndef NVGPU_ACR_LSFM_H -#define NVGPU_ACR_LSFM_H -#ifndef NVGPU_ACR_H -#warning "acr_lsfm.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif +#ifndef ACR_BLOB_CONSTRUCT_V1_H +#define ACR_BLOB_CONSTRUCT_V1_H -/* - * READ/WRITE masks for WPR region - */ -/* Readable only from level 2 and 3 client */ -#define LSF_WPR_REGION_RMASK (0xCU) -/* Writable only from level 2 and 3 client */ -#define LSF_WPR_REGION_WMASK (0xCU) -/* Readable only from level 3 client */ -#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8U) -/* Writable only from level 3 client */ -#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8U) -/* Disallow read mis-match for all clients */ -#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0U) -/* Disallow write mis-match for all clients */ -#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0U) - -/* - * Light Secure Falcon Ucode Description Defines - * This structure is prelim and may change as the ucode signing flow evolves. - */ -struct lsf_ucode_desc { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; -}; - -struct lsf_ucode_desc_v1 { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; - u32 bsupports_versioning; - u32 version; - u32 dep_map_count; - u8 dep_map[FALCON_ID_END * 2 * 4]; - u8 kdf[16]; -}; - -/* - * Light Secure WPR Header - * Defines state allowing Light Secure Falcon bootstrapping. - */ -struct lsf_wpr_header { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 status; -}; - -struct lsf_wpr_header_v1 { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 bin_version; - u32 status; -}; - - -/* - * LSF shared SubWpr Header - * - * use_case_id - Shared SubWpr use case ID (updated by nvgpu) - * start_addr - start address of subWpr (updated by nvgpu) - * size_4K - size of subWpr in 4K (updated by nvgpu) - */ -struct lsf_shared_sub_wpr_header { - u32 use_case_id; - u32 start_addr; - u32 size_4K; -}; - -/* shared sub_wpr use case IDs */ -enum { - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2 -}; - -#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \ - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA - -#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFFU) - -#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \ - LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX - -/* Static sizes of shared subWPRs */ -/* Minimum granularity supported is 4K */ -/* 1MB in 4K */ -#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100U) -/* 4K */ -#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1U) - -/* - * Bootstrap Owner Defines - */ -#define LSF_BOOTSTRAP_OWNER_DEFAULT (FALCON_ID_PMU) - -/* - * Image Status Defines - */ -#define LSF_IMAGE_STATUS_NONE (0U) -#define LSF_IMAGE_STATUS_COPY (1U) -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U) -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U) -#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U) -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U) -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U) - -/*Light Secure Bootstrap header related defines*/ -#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0U -#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE BIT32(0) -#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U -#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2) -#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3) -#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U - -/* - * Light Secure Bootstrap Header - * Defines state allowing Light Secure Falcon bootstrapping. - */ -struct lsf_lsb_header { - struct lsf_ucode_desc signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -}; - -struct lsf_lsb_header_v1 { - struct lsf_ucode_desc_v1 signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -}; +#include +#include /* * Light Secure WPR Content Alignments @@ -217,100 +59,196 @@ struct lsf_lsb_header_v1 { #define LSF_UCODE_DATA_ALIGNMENT 4096U + /* Defined for 1MB alignment */ #define SHIFT_1MB (20U) #define SHIFT_4KB (12U) /* - * Supporting maximum of 2 regions. - * This is needed to pre-allocate space in DMEM + * Maximum WPR Header size */ -#define NVGPU_FLCN_ACR_MAX_REGIONS (2U) -#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200U) +#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \ + (ALIGN_UP(((u32)sizeof(struct lsf_wpr_header_v1) * FALCON_ID_END), \ + LSF_WPR_HEADER_ALIGNMENT)) + +/* shared sub_wpr use case IDs */ +enum { + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_FRTS_VBIOS_TABLES = 1, + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA = 2 +}; + +#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX \ + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_PLAYREADY_SHARED_DATA + +#define LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_INVALID (0xFFFFFFFFU) + +#define MAX_SUPPORTED_SHARED_SUB_WPR_USE_CASES \ + LSF_SHARED_DATA_SUB_WPR_USE_CASE_ID_MAX + +/* Static sizes of shared subWPRs */ +/* Minimum granularity supported is 4K */ +/* 1MB in 4K */ +#define LSF_SHARED_DATA_SUB_WPR_FRTS_VBIOS_TABLES_SIZE_IN_4K (0x100U) +/* 4K */ +#define LSF_SHARED_DATA_SUB_WPR_PLAYREADY_SHARED_DATA_SIZE_IN_4K (0x1U) + +/*Light Secure Bootstrap header related defines*/ +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0U +#define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE BIT32(0) +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0U +#define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE BIT32(2) +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE BIT32(3) +#define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0U /* - * start_addr - Starting address of region - * end_addr - Ending address of region - * region_id - Region ID - * read_mask - Read Mask - * write_mask - WriteMask - * client_mask - Bit map of all clients currently using this region + * Image Status Defines */ -struct flcn_acr_region_prop { +#define LSF_IMAGE_STATUS_NONE (0U) +#define LSF_IMAGE_STATUS_COPY (1U) +#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2U) +#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3U) +#define LSF_IMAGE_STATUS_VALIDATION_DONE (4U) +#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U) +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U) + +struct lsf_wpr_header_v1 { + u32 falcon_id; + u32 lsb_offset; + u32 bootstrap_owner; + u32 lazy_bootstrap; + u32 bin_version; + u32 status; +}; + +struct lsf_ucode_desc_v1 { + u8 prd_keys[2][16]; + u8 dbg_keys[2][16]; + u32 b_prd_present; + u32 b_dbg_present; + u32 falcon_id; + u32 bsupports_versioning; + u32 version; + u32 dep_map_count; + u8 dep_map[FALCON_ID_END * 2 * 4]; + u8 kdf[16]; +}; + +struct lsf_lsb_header_v1 { + struct lsf_ucode_desc_v1 signature; + u32 ucode_off; + u32 ucode_size; + u32 data_size; + u32 bl_code_size; + u32 bl_imem_off; + u32 bl_data_off; + u32 bl_data_size; + u32 app_code_off; + u32 app_code_size; + u32 app_data_off; + u32 app_data_size; + u32 flags; +}; + +struct flcn_bl_dmem_desc_v1 { + u32 reserved[4]; /*Should be the first element..*/ + u32 signature[4]; /*Should be the first element..*/ + u32 ctx_dma; + struct falc_u64 code_dma_base; + u32 non_sec_code_off; + u32 non_sec_code_size; + u32 sec_code_off; + u32 sec_code_size; + u32 code_entry_point; + struct falc_u64 data_dma_base; + u32 data_size; + u32 argc; + u32 argv; +}; + +#define UCODE_NB_MAX_DATE_LENGTH 64U +struct ls_falcon_ucode_desc { + u32 descriptor_size; + u32 image_size; + u32 tools_version; + u32 app_version; + char date[UCODE_NB_MAX_DATE_LENGTH]; + u32 bootloader_start_offset; + u32 bootloader_size; + u32 bootloader_imem_offset; + u32 bootloader_entry_point; + u32 app_start_offset; + u32 app_size; + u32 app_imem_offset; + u32 app_imem_entry; + u32 app_dmem_offset; + u32 app_resident_code_offset; + u32 app_resident_code_size; + u32 app_resident_data_offset; + u32 app_resident_data_size; + u32 nb_imem_overlays; + u32 nb_dmem_overlays; + struct {u32 start; u32 size; } load_ovl[64]; + u32 compressed; +}; + +struct flcn_ucode_img_v1 { + u32 *header; + u32 *data; + struct ls_falcon_ucode_desc *desc; + u32 data_size; + void *fw_ver; + u8 load_entire_os_data; + struct lsf_ucode_desc_v1 *lsf_desc; + u8 free_res_allocs; + u32 flcn_inst; +}; + +struct lsfm_managed_ucode_img_v2 { + struct lsfm_managed_ucode_img_v2 *next; + struct lsf_wpr_header_v1 wpr_header; + struct lsf_lsb_header_v1 lsb_header; + struct flcn_bl_dmem_desc_v1 bl_gen_desc; + u32 bl_gen_desc_size; + u32 full_ucode_size; + struct flcn_ucode_img_v1 ucode_img; +}; + +/* + * LSF shared SubWpr Header + * + * use_case_id - Shared SubWpr use case ID (updated by nvgpu) + * start_addr - start address of subWpr (updated by nvgpu) + * size_4K - size of subWpr in 4K (updated by nvgpu) + */ +struct lsf_shared_sub_wpr_header { + u32 use_case_id; u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; -}; - -struct flcn_acr_region_prop_v1 { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; - u32 shadowmMem_startaddress; + u32 size_4K; }; /* - * no_regions - Number of regions used. - * region_props - Region properties + * LSFM SUB WPRs struct + * pnext : Next entry in the list, NULL if last + * sub_wpr_header : SubWpr Header struct */ -struct flcn_acr_regions { - u32 no_regions; - struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; +struct lsfm_sub_wpr { + struct lsfm_sub_wpr *pnext; + struct lsf_shared_sub_wpr_header sub_wpr_header; }; -struct flcn_acr_regions_v1 { - u32 no_regions; - struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; -}; -/* - * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons, - * and need to switch into LS mode, it needs to have its own - * actual DMEM image copied into DMEM as part of LS setup. If - * ACR desc is at location 0, it will definitely get overwritten - * causing data corruption. Hence we are reserving 0x200 bytes - * to give room for any loading data. NOTE: This has to be the - * first member always - * signature - Signature of ACR ucode. - * wpr_region_id - Region ID holding the WPR header and its details - * wpr_offset - Offset from the WPR region holding the wpr header - * regions - Region descriptors - * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob - * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob - */ -struct flcn_acr_desc { - union { - u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; - u32 signatures[4]; - } ucode_reserved_space; - /*Always 1st*/ - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; - struct flcn_acr_regions regions; - u32 nonwpr_ucode_blob_size; - u64 nonwpr_ucode_blob_start; +struct ls_flcn_mgr_v1 { + u16 managed_flcn_cnt; + u32 wpr_size; + struct lsfm_managed_ucode_img_v2 *ucode_img_list; + u16 managed_sub_wpr_count; + struct lsfm_sub_wpr *psub_wpr_list; }; -struct flcn_acr_desc_v1 { - union { - u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; - } ucode_reserved_space; - u32 signatures[4]; - /*Always 1st*/ - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; - struct flcn_acr_regions_v1 regions; - u32 nonwpr_ucode_blob_size; - u64 nonwpr_ucode_blob_start; - u32 dummy[4]; /* ACR_BSI_VPR_DESC */ -}; +int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g); +int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img); +int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img); +int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img); +int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img); -#endif /* NVGPU_ACR_LSFM_H */ +#endif /* ACR_BLOB_CONSTRUCT_V1_H */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c index 550f5f21c..da16e3b15 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c +++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.c @@ -24,13 +24,15 @@ #include #include #include -#include #include #include #include #include #include +#include "acr_bootstrap.h" +#include "acr_priv.h" + static int acr_wait_for_completion(struct gk20a *g, struct nvgpu_falcon *flcn, unsigned int timeout) { @@ -51,8 +53,8 @@ static int acr_wait_for_completion(struct gk20a *g, goto exit; } - if (g->acr.acr.acr_engine_bus_err_status != NULL) { - completion = g->acr.acr.acr_engine_bus_err_status(g, + if (g->acr->acr.acr_engine_bus_err_status != NULL) { + completion = g->acr->acr.acr_engine_bus_err_status(g, &bar0_status, &error_type); if (completion != 0) { nvgpu_err(g, "flcn-%d: ACR engine bus error", flcn_id); @@ -79,8 +81,8 @@ static int acr_wait_for_completion(struct gk20a *g, exit: if (completion != 0) { - if (g->acr.acr.report_acr_engine_bus_err_status != NULL) { - g->acr.acr.report_acr_engine_bus_err_status(g, + if (g->acr->acr.report_acr_engine_bus_err_status != NULL) { + g->acr->acr.report_acr_engine_bus_err_status(g, bar0_status, error_type); } } diff --git a/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h new file mode 100644 index 000000000..2c5511484 --- /dev/null +++ b/drivers/gpu/nvgpu/common/acr/acr_bootstrap.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef ACR_BOOTSTRAP_H +#define ACR_BOOTSTRAP_H + +/* + * Supporting maximum of 2 regions. + * This is needed to pre-allocate space in DMEM + */ +#define NVGPU_FLCN_ACR_MAX_REGIONS (2U) +#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200U) + +struct flcn_acr_region_prop { + u32 start_addr; + u32 end_addr; + u32 region_id; + u32 read_mask; + u32 write_mask; + u32 client_mask; +}; + +struct flcn_acr_regions { + u32 no_regions; + struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; +}; + +struct flcn_acr_desc { + union { + u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; + u32 signatures[4]; + } ucode_reserved_space; + /*Always 1st*/ + u32 wpr_region_id; + u32 wpr_offset; + u32 mmu_mem_range; + struct flcn_acr_regions regions; + u32 nonwpr_ucode_blob_size; + u64 nonwpr_ucode_blob_start; +}; + +/* + * start_addr - Starting address of region + * end_addr - Ending address of region + * region_id - Region ID + * read_mask - Read Mask + * write_mask - WriteMask + * client_mask - Bit map of all clients currently using this region + */ +struct flcn_acr_region_prop_v1 { + u32 start_addr; + u32 end_addr; + u32 region_id; + u32 read_mask; + u32 write_mask; + u32 client_mask; + u32 shadowmMem_startaddress; +}; + +/* + * no_regions - Number of regions used. + * region_props - Region properties + */ +struct flcn_acr_regions_v1 { + u32 no_regions; + struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; +}; + +/* + * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons, + * and need to switch into LS mode, it needs to have its own + * actual DMEM image copied into DMEM as part of LS setup. If + * ACR desc is at location 0, it will definitely get overwritten + * causing data corruption. Hence we are reserving 0x200 bytes + * to give room for any loading data. NOTE: This has to be the + * first member always + * signature - Signature of ACR ucode. + * wpr_region_id - Region ID holding the WPR header and its details + * wpr_offset - Offset from the WPR region holding the wpr header + * regions - Region descriptors + * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob + * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob + */ +struct flcn_acr_desc_v1 { + union { + u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; + } ucode_reserved_space; + u32 signatures[4]; + /*Always 1st*/ + u32 wpr_region_id; + u32 wpr_offset; + u32 mmu_mem_range; + struct flcn_acr_regions_v1 regions; + u32 nonwpr_ucode_blob_size; + u64 nonwpr_ucode_blob_start; + u32 dummy[4]; /* ACR_BSI_VPR_DESC */ +}; + +/* HS Falcon BL interfaces */ +/* + * The header used by NVGPU to figure out code and data sections of bootloader + * + * bl_code_off - Offset of code section in the image + * bl_code_size - Size of code section in the image + * bl_data_off - Offset of data section in the image + * bl_data_size - Size of data section in the image + */ +struct flcn_bl_img_hdr { + u32 bl_code_off; + u32 bl_code_size; + u32 bl_data_off; + u32 bl_data_size; +}; + +/* + * The descriptor used by NVGPU to figure out the requirements of bootloader + * + * bl_start_tag - Starting tag of bootloader + * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc + * to be loaded + * bl_img_hdr - Description of the image + */ +struct hsflcn_bl_desc { + u32 bl_start_tag; + u32 bl_desc_dmem_load_off; + struct flcn_bl_img_hdr bl_img_hdr; +}; + +struct bin_hdr { + /* 0x10de */ + u32 bin_magic; + /* versioning of bin format */ + u32 bin_ver; + /* Entire image size including this header */ + u32 bin_size; + /* + * Header offset of executable binary metadata, + * start @ offset- 0x100 * + */ + u32 header_offset; + /* + * Start of executable binary data, start @ + * offset- 0x200 + */ + u32 data_offset; + /* Size of executable binary */ + u32 data_size; +}; + +struct hs_flcn_bl { + const char *bl_fw_name; + struct nvgpu_firmware *hs_bl_fw; + struct hsflcn_bl_desc *hs_bl_desc; + struct bin_hdr *hs_bl_bin_hdr; + struct nvgpu_mem hs_bl_ucode; +}; + +struct acr_fw_header { + u32 sig_dbg_offset; + u32 sig_dbg_size; + u32 sig_prod_offset; + u32 sig_prod_size; + u32 patch_loc; + u32 patch_sig; + u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */ + u32 hdr_size; /* Size of above header */ +}; + + +#endif /* ACR_BOOTSTRAP_H */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_gm20b.c b/drivers/gpu/nvgpu/common/acr/acr_gm20b.c index 0b20adece..80989e18d 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gm20b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_gm20b.c @@ -20,16 +20,16 @@ * DEALINGS IN THE SOFTWARE. */ -#include -#include -#include -#include -#include #include +#include +#include +#include #include #include "common/pmu/pmu_gm20b.h" +#include "acr_blob_construct_v0.h" +#include "acr_priv.h" #include "acr_gm20b.h" static int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g, @@ -66,10 +66,10 @@ static int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g, &(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]); acr_dmem_desc->nonwpr_ucode_blob_start = - nvgpu_mem_get_addr(g, &g->acr.ucode_blob); - nvgpu_assert(g->acr.ucode_blob.size <= U32_MAX); + nvgpu_mem_get_addr(g, &g->acr->ucode_blob); + nvgpu_assert(g->acr->ucode_blob.size <= U32_MAX); acr_dmem_desc->nonwpr_ucode_blob_size = - (u32)g->acr.ucode_blob.size; + (u32)g->acr->ucode_blob.size; acr_dmem_desc->regions.no_regions = 1U; acr_dmem_desc->wpr_offset = 0U; } @@ -174,28 +174,6 @@ static void gm20b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr) gk20a_pmu_bar0_error_status; } -void gm20b_remove_acr_support(struct nvgpu_acr *acr) -{ - struct gk20a *g = acr->g; - struct mm_gk20a *mm = &g->mm; - struct vm_gk20a *vm = mm->pmu.vm; - - if (acr->acr.acr_fw != NULL) { - nvgpu_release_firmware(g, acr->acr.acr_fw); - } - - if (acr->acr.acr_hs_bl.hs_bl_fw != NULL) { - nvgpu_release_firmware(g, acr->acr.acr_hs_bl.hs_bl_fw); - } - - if (nvgpu_mem_is_valid(&acr->acr.acr_ucode)) { - nvgpu_dma_unmap_free(vm, &acr->acr.acr_ucode); - } - if (nvgpu_mem_is_valid(&acr->acr.acr_hs_bl.hs_bl_ucode)) { - nvgpu_dma_unmap_free(vm, &acr->acr.acr_hs_bl.hs_bl_ucode); - } -} - void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) { nvgpu_log_fn(g, " "); @@ -216,6 +194,4 @@ void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) gm20b_acr_patch_wpr_info_to_ucode; acr->acr_fill_bl_dmem_desc = gm20b_acr_fill_bl_dmem_desc; - - acr->remove_support = gm20b_remove_acr_support; } diff --git a/drivers/gpu/nvgpu/common/acr/acr_gm20b.h b/drivers/gpu/nvgpu/common/acr/acr_gm20b.h index cdb4cf837..0b7166d94 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gm20b.h +++ b/drivers/gpu/nvgpu/common/acr/acr_gm20b.h @@ -1,7 +1,7 @@ /* * GM20B ACR * - * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,7 +25,6 @@ #ifndef NVGPU_GM20B_ACR_GM20B_H #define NVGPU_GM20B_ACR_GM20B_H -void gm20b_remove_acr_support(struct nvgpu_acr *acr); void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); #endif /*NVGPU_GM20B_ACR_GM20B_H*/ diff --git a/drivers/gpu/nvgpu/common/acr/acr_gp10b.c b/drivers/gpu/nvgpu/common/acr/acr_gp10b.c index 88b4cf921..fe1740b56 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gp10b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_gp10b.c @@ -21,10 +21,12 @@ */ #include -#include #include #include +#include "acr_blob_construct_v0.h" +#include "acr_priv.h" + #include "acr_gm20b.h" #include "acr_gp10b.h" diff --git a/drivers/gpu/nvgpu/common/acr/acr_gv100.c b/drivers/gpu/nvgpu/common/acr/acr_gv100.c index 3fdedd300..8cfb5c958 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gv100.c +++ b/drivers/gpu/nvgpu/common/acr/acr_gv100.c @@ -20,14 +20,14 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include -#include #include #include -#include "acr_gm20b.h" +#include "acr_blob_construct_v1.h" +#include "acr_priv.h" #include "acr_gv100.h" + #include "gp106/sec2_gp106.h" @@ -207,8 +207,5 @@ void nvgpu_gv100_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) acr->bootstrap_hs_acr = nvgpu_acr_bootstrap_hs_ucode; acr->patch_wpr_info_to_ucode = gv100_acr_patch_wpr_info_to_ucode; - acr->acr_fill_bl_dmem_desc = - gv100_acr_fill_bl_dmem_desc; - - acr->remove_support = gm20b_remove_acr_support; + acr->acr_fill_bl_dmem_desc = gv100_acr_fill_bl_dmem_desc; } diff --git a/drivers/gpu/nvgpu/common/acr/acr_gv100.h b/drivers/gpu/nvgpu/common/acr/acr_gv100.h index c24dfa134..ea8441a48 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gv100.h +++ b/drivers/gpu/nvgpu/common/acr/acr_gv100.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,9 +23,6 @@ #ifndef NVGPU_ACR_GV100_H #define NVGPU_ACR_GV100_H -#define GV100_FECS_UCODE_SIG "gv100/fecs_sig.bin" -#define GV100_GPCCS_UCODE_SIG "gv100/gpccs_sig.bin" - int gv100_acr_fill_bl_dmem_desc(struct gk20a *g, struct nvgpu_acr *acr, struct hs_acr *acr_desc, u32 *acr_ucode_header); diff --git a/drivers/gpu/nvgpu/common/acr/acr_gv11b.c b/drivers/gpu/nvgpu/common/acr/acr_gv11b.c index 0789a8e4c..7ac17f033 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_gv11b.c +++ b/drivers/gpu/nvgpu/common/acr/acr_gv11b.c @@ -22,12 +22,14 @@ #include #include -#include #include #include #include "common/pmu/pmu_gm20b.h" +#include "acr_blob_construct_v1.h" +#include "acr_priv.h" + #include "acr_gm20b.h" #include "acr_gv100.h" #include "acr_gv11b.h" @@ -66,10 +68,10 @@ static int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, &(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]); acr_dmem_desc->nonwpr_ucode_blob_start = - nvgpu_mem_get_addr(g, &g->acr.ucode_blob); - nvgpu_assert(g->acr.ucode_blob.size <= U32_MAX); + nvgpu_mem_get_addr(g, &g->acr->ucode_blob); + nvgpu_assert(g->acr->ucode_blob.size <= U32_MAX); acr_dmem_desc->nonwpr_ucode_blob_size = - (u32)g->acr.ucode_blob.size; + (u32)g->acr->ucode_blob.size; acr_dmem_desc->regions.no_regions = 1U; acr_dmem_desc->wpr_offset = 0U; } @@ -186,8 +188,5 @@ void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_sys; acr->bootstrap_hs_acr = nvgpu_acr_bootstrap_hs_ucode; acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode; - acr->acr_fill_bl_dmem_desc = - gv100_acr_fill_bl_dmem_desc; - - acr->remove_support = gm20b_remove_acr_support; + acr->acr_fill_bl_dmem_desc = gv100_acr_fill_bl_dmem_desc; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/common/acr/acr_priv.h similarity index 69% rename from drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h rename to drivers/gpu/nvgpu/common/acr/acr_priv.h index 7bb15b75b..01477d1b4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h +++ b/drivers/gpu/nvgpu/common/acr/acr_priv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,24 +20,58 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef NVGPU_ACR_H -#define NVGPU_ACR_H +#ifndef ACR_H +#define ACR_H #include +#include -#include "gk20a/mm_gk20a.h" - -#include "acr_lsfm.h" -#include "acr_flcnbl.h" -#include "acr_objlsfm.h" -#include "acr_objflcn.h" +#include "acr_bootstrap.h" +#include "acr_blob_construct_v0.h" +#include "acr_blob_construct_v1.h" struct nvgpu_firmware; struct gk20a; -struct hs_acr_ops; -struct hs_acr; struct nvgpu_acr; +#define nvgpu_acr_dbg(g, fmt, args...) \ + nvgpu_log(g, gpu_dbg_pmu, fmt, ##args) + +/* + * Falcon UCODE header index. + */ +#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0U) +#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1U) +#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2U) +#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3U) +#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4U) + +/* + * There are total N number of Apps with code and offset defined in UCODE header + * This macro provides the CODE and DATA offset and size of Ath application. + */ +#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5U) +#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \ + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((A)*2U)) +#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \ + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((A)*2U) + 1U) +#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((N)*2U) - 1U) + +#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1U) +#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \ + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((A)*2U)) +#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \ + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((A)*2U) + 1U) +#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((N)*2U) - 1U) + +#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1U) +#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ + (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2U) + #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" #define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" @@ -48,74 +82,29 @@ struct nvgpu_acr; #define GM20B_FECS_UCODE_SIG "fecs_sig.bin" #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin" +#define GV100_FECS_UCODE_SIG "gv100/fecs_sig.bin" +#define GV100_GPCCS_UCODE_SIG "gv100/gpccs_sig.bin" + +#define TU104_FECS_UCODE_SIG "tu104/fecs_sig.bin" +#define TU104_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin" + #define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin" #define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin" #define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin" #define ACR_COMPLETION_TIMEOUT_MS 10000U /*in msec */ -#define nvgpu_acr_dbg(g, fmt, args...) \ - nvgpu_log(g, gpu_dbg_pmu, fmt, ##args) - -struct bin_hdr { - /* 0x10de */ - u32 bin_magic; - /* versioning of bin format */ - u32 bin_ver; - /* Entire image size including this header */ - u32 bin_size; - /* - * Header offset of executable binary metadata, - * start @ offset- 0x100 * - */ - u32 header_offset; - /* - * Start of executable binary data, start @ - * offset- 0x200 - */ - u32 data_offset; - /* Size of executable binary */ - u32 data_size; -}; - -struct acr_fw_header { - u32 sig_dbg_offset; - u32 sig_dbg_size; - u32 sig_prod_offset; - u32 sig_prod_size; - u32 patch_loc; - u32 patch_sig; - u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */ - u32 hdr_size; /* Size of above header */ -}; - struct wpr_carveout_info { u64 wpr_base; u64 nonwpr_base; u64 size; }; -/* ACR interfaces */ - -struct acr_lsf_config { - u32 falcon_id; - u32 falcon_dma_idx; - bool is_lazy_bootstrap; - bool is_priv_load; - - int (*get_lsf_ucode_details)(struct gk20a *g, void *lsf_ucode_img); - void (*get_cmd_line_args_offset)(struct gk20a *g, u32 *args_offset); -}; - -struct hs_flcn_bl { - const char *bl_fw_name; - struct nvgpu_firmware *hs_bl_fw; - struct hsflcn_bl_desc *hs_bl_desc; - struct bin_hdr *hs_bl_bin_hdr; - struct nvgpu_mem hs_bl_ucode; -}; - +/* ACR Falcon descriptor's */ struct hs_acr { +#define ACR_DEFAULT 0U +#define ACR_AHESASC 1U +#define ACR_ASB 2U u32 acr_type; /* HS bootloader to validate & load ACR ucode */ @@ -150,15 +139,22 @@ struct hs_acr { u32 *error_type); }; -#define ACR_DEFAULT 0U -#define ACR_AHESASC 1U -#define ACR_ASB 2U +struct acr_lsf_config { + u32 falcon_id; + u32 falcon_dma_idx; + bool is_lazy_bootstrap; + bool is_priv_load; + + int (*get_lsf_ucode_details)(struct gk20a *g, void *lsf_ucode_img); + void (*get_cmd_line_args_offset)(struct gk20a *g, u32 *args_offset); +}; struct nvgpu_acr { struct gk20a *g; u32 bootstrap_owner; + /* LSF properties */ u32 lsf_enable_mask; struct acr_lsf_config lsf[FALCON_ID_END]; @@ -182,7 +178,6 @@ struct nvgpu_acr { struct hs_acr acr_asb; int (*prepare_ucode_blob)(struct gk20a *g); - void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); int (*alloc_blob_space)(struct gk20a *g, size_t size, struct nvgpu_mem *mem); int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr, @@ -193,7 +188,7 @@ struct nvgpu_acr { int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr, struct hs_acr *acr_desc); - void (*remove_support)(struct nvgpu_acr *acr); + void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); }; int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr, @@ -205,23 +200,4 @@ int nvgpu_acr_alloc_blob_space_vid(struct gk20a *g, size_t size, void nvgpu_acr_wpr_info_sys(struct gk20a *g, struct wpr_carveout_info *inf); void nvgpu_acr_wpr_info_vid(struct gk20a *g, struct wpr_carveout_info *inf); -int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g); -int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g); - -int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img); -int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img); -int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img); - -int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img); -int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img); -int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img); -int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img); - -void nvgpu_acr_init(struct gk20a *g); -int nvgpu_acr_construct_execute(struct gk20a *g); - -int nvgpu_acr_self_hs_load_bootstrap(struct gk20a *g, struct nvgpu_falcon *flcn, - struct nvgpu_firmware *hs_fw, u32 timeout); - -#endif /* NVGPU_ACR_H */ - +#endif /* ACR_H */ diff --git a/drivers/gpu/nvgpu/common/acr/acr_tu104.c b/drivers/gpu/nvgpu/common/acr/acr_tu104.c index b2deea922..58fde3e61 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_tu104.c +++ b/drivers/gpu/nvgpu/common/acr/acr_tu104.c @@ -20,15 +20,12 @@ * DEALINGS IN THE SOFTWARE. */ -#include -#include -#include -#include -#include #include +#include #include -#include "acr_gm20b.h" +#include "acr_blob_construct_v1.h" +#include "acr_priv.h" #include "acr_gv100.h" #include "acr_tu104.h" @@ -43,12 +40,12 @@ static int tu104_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr, nvgpu_log_fn(g, " "); - err = nvgpu_acr_bootstrap_hs_ucode(g, &g->acr, &g->acr.acr_ahesasc); + err = nvgpu_acr_bootstrap_hs_ucode(g, g->acr, &g->acr->acr_ahesasc); if (err != 0) { nvgpu_err(g, "ACR AHESASC bootstrap failed"); goto exit; } - err = nvgpu_acr_bootstrap_hs_ucode(g, &g->acr, &g->acr.acr_asb); + err = nvgpu_acr_bootstrap_hs_ucode(g, g->acr, &g->acr->acr_asb); if (err != 0) { nvgpu_err(g, "ACR ASB bootstrap failed"); goto exit; @@ -121,37 +118,6 @@ static void nvgpu_tu104_acr_asb_sw_init(struct gk20a *g, gv100_gsp_setup_hw_and_bl_bootstrap; } -static void tu104_free_hs_acr(struct gk20a *g, - struct hs_acr *acr_type) -{ - struct mm_gk20a *mm = &g->mm; - struct vm_gk20a *vm = mm->pmu.vm; - - if (acr_type->acr_fw != NULL) { - nvgpu_release_firmware(g, acr_type->acr_fw); - } - - if (acr_type->acr_hs_bl.hs_bl_fw != NULL) { - nvgpu_release_firmware(g, acr_type->acr_hs_bl.hs_bl_fw); - } - - if (nvgpu_mem_is_valid(&acr_type->acr_ucode)) { - nvgpu_dma_unmap_free(vm, &acr_type->acr_ucode); - } - if (nvgpu_mem_is_valid(&acr_type->acr_hs_bl.hs_bl_ucode)) { - nvgpu_dma_unmap_free(vm, &acr_type->acr_hs_bl.hs_bl_ucode); - } -} - -static void tu104_remove_acr_support(struct nvgpu_acr *acr) -{ - struct gk20a *g = acr->g; - - tu104_free_hs_acr(g, &acr->acr_ahesasc); - - tu104_free_hs_acr(g, &acr->acr_asb); -} - void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) { nvgpu_log_fn(g, " "); @@ -165,7 +131,6 @@ void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v1; acr->bootstrap_owner = FALCON_ID_GSPLITE; acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr; - acr->remove_support = tu104_remove_acr_support; /* Init ACR-AHESASC */ nvgpu_tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc); diff --git a/drivers/gpu/nvgpu/common/acr/acr_tu104.h b/drivers/gpu/nvgpu/common/acr/acr_tu104.h index b64b9e6ae..772457947 100644 --- a/drivers/gpu/nvgpu/common/acr/acr_tu104.h +++ b/drivers/gpu/nvgpu/common/acr/acr_tu104.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,9 +23,6 @@ #ifndef NVGPU_ACR_TU104_H #define NVGPU_ACR_TU104_H -#define TU104_FECS_UCODE_SIG "tu104/fecs_sig.bin" -#define TU104_GPCCS_UCODE_SIG "tu104/gpccs_sig.bin" - void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr); #endif /*NVGPU_ACR_TU104_H*/ diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 686ac9a6c..c60dc1bcb 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -196,7 +196,11 @@ int gk20a_finalize_poweron(struct gk20a *g) if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { /* Init chip specific ACR properties */ - nvgpu_acr_init(g); + err = nvgpu_acr_init(g, &g->acr); + if (err != 0) { + nvgpu_err(g, "ACR init failed %d", err); + goto done; + } } if (g->ops.bios.init != NULL) { @@ -311,7 +315,7 @@ int gk20a_finalize_poweron(struct gk20a *g) if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { /* construct ucode blob, load & bootstrap LSF's using HS ACR */ - err = nvgpu_acr_construct_execute(g); + err = nvgpu_acr_construct_execute(g, g->acr); if (err != 0) { nvgpu_mutex_release(&g->tpc_pg_lock); goto done; diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c index fff41f92b..9412e774d 100644 --- a/drivers/gpu/nvgpu/common/mm/mm.c +++ b/drivers/gpu/nvgpu/common/mm/mm.c @@ -445,9 +445,8 @@ static int nvgpu_init_mm_setup_sw(struct gk20a *g) * allocated before all other buffers */ - if (g->acr.alloc_blob_space != NULL && - !nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY)) { - err = g->acr.alloc_blob_space(g, 0, &g->acr.ucode_blob); + if (!nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY)) { + err = nvgpu_acr_alloc_blob_prerequisite(g, g->acr, 0); if (err != 0) { return err; } diff --git a/drivers/gpu/nvgpu/common/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/vgpu/vgpu.c index f8cc1f9d1..e38c2e434 100644 --- a/drivers/gpu/nvgpu/common/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/vgpu.c @@ -237,10 +237,6 @@ void vgpu_remove_support_common(struct gk20a *g) g->pmu.remove_support(&g->pmu); } - if (g->acr.remove_support != NULL) { - g->acr.remove_support(&g->acr); - } - if (g->gr.remove_support) { g->gr.remove_support(&g->gr); } diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 3cf893ab3..52aac2c4a 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -775,7 +775,7 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) BIT32(FALCON_ID_FECS) | BIT32(FALCON_ID_GPCCS)); } else { - err = g->acr.bootstrap_hs_acr(g, &g->acr, &g->acr.acr); + err = nvgpu_acr_bootstrap_hs_acr(g, g->acr); if (err != 0) { nvgpu_err(g, "GR Recovery: ACR GR LSF bootstrap failed"); } @@ -794,10 +794,10 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) } else { /* bind WPR VA inst block */ gr_gk20a_load_falcon_bind_instblk(g); - if (g->acr.lsf[FALCON_ID_FECS].is_lazy_bootstrap) { + if (nvgpu_acr_is_lsf_lazy_bootstrap(g, g->acr, FALCON_ID_FECS)) { falcon_id_mask |= BIT8(FALCON_ID_FECS); } - if (g->acr.lsf[FALCON_ID_GPCCS].is_lazy_bootstrap) { + if (nvgpu_acr_is_lsf_lazy_bootstrap(g, g->acr, FALCON_ID_GPCCS)) { falcon_id_mask |= BIT8(FALCON_ID_GPCCS); } diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gv100.c b/drivers/gpu/nvgpu/hal/fb/fb_gv100.c index c245920c6..ea2da733f 100644 --- a/drivers/gpu/nvgpu/hal/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/hal/fb/fb_gv100.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -40,6 +39,7 @@ #include #include #include +#include #include "fb_gv100.h" diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr.h new file mode 100644 index 000000000..d0bb01e7e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/acr.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_ACR_H +#define NVGPU_ACR_H + +struct gk20a; +struct nvgpu_falcon; +struct nvgpu_firmware; +struct nvgpu_acr; + +int nvgpu_acr_init(struct gk20a *g, struct nvgpu_acr **acr); +int nvgpu_acr_alloc_blob_prerequisite(struct gk20a *g, struct nvgpu_acr *acr, + size_t size); +int nvgpu_acr_construct_execute(struct gk20a *g, struct nvgpu_acr *acr); +int nvgpu_acr_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr); +bool nvgpu_acr_is_lsf_lazy_bootstrap(struct gk20a *g, struct nvgpu_acr *acr, + u32 falcon_id); + +int nvgpu_acr_self_hs_load_bootstrap(struct gk20a *g, struct nvgpu_falcon *flcn, + struct nvgpu_firmware *hs_fw, u32 timeout); + +#endif /* NVGPU_ACR_H */ + diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h deleted file mode 100644 index ad697b2b7..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_FLCNBL_H -#define NVGPU_ACR_FLCNBL_H - -#include - -#ifndef NVGPU_ACR_H -#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -/* - * Structure used by the boot-loader to load the rest of the code. This has - * to be filled by NVGPU and copied into DMEM at offset provided in the - * hsflcn_bl_desc.bl_desc_dmem_load_off. - */ -struct flcn_bl_dmem_desc { - u32 reserved[4]; /*Should be the first element..*/ - u32 signature[4]; /*Should be the first element..*/ - u32 ctx_dma; - u32 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - u32 data_dma_base; - u32 data_size; - u32 code_dma_base1; - u32 data_dma_base1; -}; - -struct flcn_bl_dmem_desc_v1 { - u32 reserved[4]; /*Should be the first element..*/ - u32 signature[4]; /*Should be the first element..*/ - u32 ctx_dma; - struct falc_u64 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - struct falc_u64 data_dma_base; - u32 data_size; - u32 argc; - u32 argv; -}; - -/* - * The header used by NVGPU to figure out code and data sections of bootloader - * - * bl_code_off - Offset of code section in the image - * bl_code_size - Size of code section in the image - * bl_data_off - Offset of data section in the image - * bl_data_size - Size of data section in the image - */ -struct flcn_bl_img_hdr { - u32 bl_code_off; - u32 bl_code_size; - u32 bl_data_off; - u32 bl_data_size; -}; - -/* - * The descriptor used by NVGPU to figure out the requirements of bootloader - * - * bl_start_tag - Starting tag of bootloader - * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc - * to be loaded - * bl_img_hdr - Description of the image - */ -struct hsflcn_bl_desc { - u32 bl_start_tag; - u32 bl_desc_dmem_load_off; - struct flcn_bl_img_hdr bl_img_hdr; -}; - -/* - * Legacy structure used by the current PMU/DPU bootloader. - */ -struct loader_config { - u32 dma_idx; - u32 code_dma_base; /* upper 32-bits of 40-bit dma address */ - u32 code_size_total; - u32 code_size_to_load; - u32 code_entry_point; - u32 data_dma_base; /* upper 32-bits of 40-bit dma address */ - u32 data_size; /* initialized data of the application */ - u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */ - u32 argc; - u32 argv; - u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */ - u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */ - u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */ -}; - -struct loader_config_v1 { - u32 reserved; - u32 dma_idx; - struct falc_u64 code_dma_base; - u32 code_size_total; - u32 code_size_to_load; - u32 code_entry_point; - struct falc_u64 data_dma_base; - u32 data_size; - struct falc_u64 overlay_dma_base; - u32 argc; - u32 argv; -}; - -/* - * Union of all supported structures used by bootloaders. - */ -union flcn_bl_generic_desc { - struct flcn_bl_dmem_desc bl_dmem_desc; - struct loader_config loader_cfg; -}; - -union flcn_bl_generic_desc_v1 { - struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; - struct loader_config_v1 loader_cfg_v1; -}; - -#endif /* NVGPU_ACR_FLCNBL_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h deleted file mode 100644 index 1d6ef5674..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_OBJFLCN_H -#define NVGPU_ACR_OBJFLCN_H - -#ifndef NVGPU_ACR_H -#warning "acr_objflcn.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -struct flcn_ucode_img { - u32 *header; /* only some falcons have header */ - u32 *data; - struct pmu_ucode_desc *desc; /* only some falcons have descriptor */ - u32 data_size; - void *fw_ver; /* CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct */ - u8 load_entire_os_data; /* load the whole osData section at boot time.*/ - /* NULL if not a light secure falcon.*/ - struct lsf_ucode_desc *lsf_desc; - /* True if there a resources to freed by the client. */ - u8 free_res_allocs; - u32 flcn_inst; -}; - -struct flcn_ucode_img_v1 { - u32 *header; - u32 *data; - struct pmu_ucode_desc_v1 *desc; - u32 data_size; - void *fw_ver; - u8 load_entire_os_data; - struct lsf_ucode_desc_v1 *lsf_desc; - u8 free_res_allocs; - u32 flcn_inst; -}; - -/* - * Falcon UCODE header index. - */ -#define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0U) -#define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1U) -#define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2U) -#define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3U) -#define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4U) - -/* - * There are total N number of Apps with code and offset defined in UCODE header - * This macro provides the CODE and DATA offset and size of Ath application. - */ -#define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5U) -#define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((A)*2U)) -#define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((A)*2U) + 1U) -#define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + ((N)*2U) - 1U) - -#define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1U) -#define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((A)*2U)) -#define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((A)*2U) + 1U) -#define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + ((N)*2U) - 1U) - -#define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1U) -#define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ - (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2U) - -#endif /* NVGPU_ACR_OBJFLCN_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h deleted file mode 100644 index e3769bb74..000000000 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef NVGPU_ACR_OBJLSFM_H -#define NVGPU_ACR_OBJLSFM_H - -#ifndef NVGPU_ACR_H -#warning "acr_objlsfm.h not included from nvgpu_acr.h!" \ - "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" -#endif - -#include "acr_flcnbl.h" -#include "acr_objflcn.h" - -/* - * LSFM Managed Ucode Image - * next : Next image the list, NULL if last. - * wpr_header : WPR header for this ucode image - * lsb_header : LSB header for this ucode image - * bl_gen_desc : Bootloader generic desc structure for this ucode image - * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image - * full_ucode_size : Surface size required for final ucode image - * ucode_img : Ucode image info - */ -struct lsfm_managed_ucode_img { - struct lsfm_managed_ucode_img *next; - struct lsf_wpr_header wpr_header; - struct lsf_lsb_header lsb_header; - union flcn_bl_generic_desc bl_gen_desc; - u32 bl_gen_desc_size; - u32 full_ucode_size; - struct flcn_ucode_img ucode_img; -}; - -struct lsfm_managed_ucode_img_v2 { - struct lsfm_managed_ucode_img_v2 *next; - struct lsf_wpr_header_v1 wpr_header; - struct lsf_lsb_header_v1 lsb_header; - union flcn_bl_generic_desc_v1 bl_gen_desc; - u32 bl_gen_desc_size; - u32 full_ucode_size; - struct flcn_ucode_img_v1 ucode_img; -}; - -/* - * Defines the structure used to contain all generic information related to - * the LSFM. - * Contains the Light Secure Falcon Manager (LSFM) feature related data. - */ -struct ls_flcn_mgr { - u16 managed_flcn_cnt; - u32 wpr_size; - u32 disable_mask; - struct lsfm_managed_ucode_img *ucode_img_list; - void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ -}; - -/* - * LSFM SUB WPRs struct - * pnext : Next entry in the list, NULL if last - * sub_wpr_header : SubWpr Header struct - */ -struct lsfm_sub_wpr { - struct lsfm_sub_wpr *pnext; - struct lsf_shared_sub_wpr_header sub_wpr_header; -}; - -struct ls_flcn_mgr_v1 { - u16 managed_flcn_cnt; - u32 wpr_size; - u32 disable_mask; - struct lsfm_managed_ucode_img_v2 *ucode_img_list; - void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ - u16 managed_sub_wpr_count; - struct lsfm_sub_wpr *psub_wpr_list; -}; - - -#endif /* NVGPU_ACR_OBJLSFM_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index b87e912a7..a82c003b7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -81,7 +81,7 @@ struct nvgpu_cbc; #include #include #include -#include +#include #include #include #include @@ -1820,7 +1820,7 @@ struct gk20a { struct sim_nvgpu *sim; struct mm_gk20a mm; struct nvgpu_pmu pmu; - struct nvgpu_acr acr; + struct nvgpu_acr *acr; struct nvgpu_ecc ecc; struct nvgpu_clk_pmupstate *clk_pmu; struct perf_pmupstate *perf_pmu; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 38ff3ab39..c7dd79695 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -260,31 +260,6 @@ struct pmu_ucode_desc { u32 compressed; }; -struct pmu_ucode_desc_v1 { - u32 descriptor_size; - u32 image_size; - u32 tools_version; - u32 app_version; - char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH]; - u32 bootloader_start_offset; - u32 bootloader_size; - u32 bootloader_imem_offset; - u32 bootloader_entry_point; - u32 app_start_offset; - u32 app_size; - u32 app_imem_offset; - u32 app_imem_entry; - u32 app_dmem_offset; - u32 app_resident_code_offset; - u32 app_resident_code_size; - u32 app_resident_data_offset; - u32 app_resident_data_size; - u32 nb_imem_overlays; - u32 nb_dmem_overlays; - struct {u32 start; u32 size; } load_ovl[64]; - u32 compressed; -}; - struct pmu_mutex { u32 id; u32 index; diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c index 4a7b9a524..801b3de67 100644 --- a/drivers/gpu/nvgpu/os/linux/module.c +++ b/drivers/gpu/nvgpu/os/linux/module.c @@ -763,10 +763,6 @@ void gk20a_remove_support(struct gk20a *g) g->sec2.remove_support(&g->sec2); } - if (g->acr.remove_support != NULL) { - g->acr.remove_support(&g->acr); - } - if (g->gr.remove_support) g->gr.remove_support(&g->gr);