From 10fae67c21577fe45338c53e5e1b3f2235304668 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Sat, 15 Jun 2019 18:49:17 +0530 Subject: [PATCH] gpu: nvgpu: add flag for debugger fields in struct gk20a Add CONFIG_NVGPU_DEBUGGER flag for debugger specific fields in struct gk20a Jira NVGPU-3506 Change-Id: Icfae87e16e0079a2c5f16714b8a8ced7c6572cd4 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2137254 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/rc/rc.c | 4 +++ drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c | 4 +++ drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c | 4 +++ drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 30 +++++++++++-------- 4 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/common/rc/rc.c b/drivers/gpu/nvgpu/common/rc/rc.c index 7ca665907..88621a0e1 100644 --- a/drivers/gpu/nvgpu/common/rc/rc.c +++ b/drivers/gpu/nvgpu/common/rc/rc.c @@ -174,7 +174,9 @@ void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg, u32 eng_bitmask = 0U; int err = 0; +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_acquire(&g->dbg_sessions_lock); +#endif /* disable tsg so that it does not get scheduled again */ g->ops.tsg.disable(tsg); @@ -234,5 +236,7 @@ void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg, nvgpu_tsg_abort(g, tsg, false); } +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_release(&g->dbg_sessions_lock); +#endif } diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c index b41487639..6bf140748 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c @@ -601,7 +601,9 @@ u32 gm20b_gr_intr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 s nvgpu_safe_mult_u32(gpc_stride, gpc), nvgpu_safe_mult_u32(tpc_in_gpc_stride, tpc)); +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_acquire(&g->dbg_sessions_lock); +#endif sm_id = gr_gpc0_tpc0_sm_cfg_sm_id_v( gk20a_readl(g, nvgpu_safe_add_u32( @@ -620,7 +622,9 @@ u32 gm20b_gr_intr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 s gm20b_gr_intr_read_sm_error_state(g, offset, sm_error_states); record_fail: +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_release(&g->dbg_sessions_lock); +#endif return sm_id; } diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c index c802cd68f..c129557be 100644 --- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c +++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c @@ -1477,7 +1477,9 @@ u32 gv11b_gr_intr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 s struct nvgpu_tsg_sm_error_state *sm_error_states = NULL; struct nvgpu_tsg *tsg = NULL; +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_acquire(&g->dbg_sessions_lock); +#endif sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); gpc_offset = nvgpu_gr_gpc_offset(g, gpc); @@ -1506,7 +1508,9 @@ u32 gv11b_gr_intr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 s gv11b_gr_intr_read_sm_error_state(g, offset, sm_error_states); record_fail: +#ifdef CONFIG_NVGPU_DEBUGGER nvgpu_mutex_release(&g->dbg_sessions_lock); +#endif return sm_id; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index a83b9f882..33dc3a981 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1962,6 +1962,7 @@ struct gk20a { */ struct nvgpu_semaphore_sea *sema_sea; +#ifdef CONFIG_NVGPU_DEBUGGER /* held while manipulating # of debug/profiler sessions present */ /* also prevents debug sessions from attaching until released */ struct nvgpu_mutex dbg_sessions_lock; @@ -1969,16 +1970,9 @@ struct gk20a { /*refcount for timeout disable */ nvgpu_atomic_t timeouts_disabled_refcount; -#ifdef CONFIG_NVGPU_DEBUGGER /* must have dbg_sessions_lock before use */ struct nvgpu_dbg_reg_op *dbg_regops_tmp_buf; u32 dbg_regops_tmp_buf_ops; -#endif - -#if defined(CONFIG_NVGPU_CYCLESTATS) - struct nvgpu_mutex cs_lock; - struct gk20a_cs_snapshot *cs_data; -#endif /* For perfbuf mapping */ struct { @@ -1991,6 +1985,19 @@ struct gk20a { bool global_profiler_reservation_held; int profiler_reservation_count; + bool mmu_debug_ctrl; +#endif /* CONFIG_NVGPU_DEBUGGER */ + +#ifdef CONFIG_NVGPU_FECS_TRACE + struct gk20a_ctxsw_trace *ctxsw_trace; + struct nvgpu_gr_fecs_trace *fecs_trace; +#endif + +#ifdef CONFIG_NVGPU_CYCLESTATS + struct nvgpu_mutex cs_lock; + struct gk20a_cs_snapshot *cs_data; +#endif + void (*remove_support)(struct gk20a *g); u64 pg_ingating_time_us; @@ -2070,11 +2077,6 @@ struct gk20a { struct gk20a_scale_profile *scale_profile; unsigned long last_freq; - struct gk20a_ctxsw_trace *ctxsw_trace; - struct nvgpu_gr_fecs_trace *fecs_trace; - - bool mmu_debug_ctrl; - u32 tpc_fs_mask_user; u32 tpc_pg_mask; @@ -2150,7 +2152,11 @@ struct gk20a { static inline bool nvgpu_is_timeouts_enabled(struct gk20a *g) { +#ifdef CONFIG_NVGPU_DEBUGGER return nvgpu_atomic_read(&g->timeouts_disabled_refcount) == 0; +#else + return true; +#endif } #define POLL_DELAY_MIN_US 10U