diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
index 4af1c0922..8987714fa 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.c
@@ -1457,3 +1457,25 @@ int vgpu_gr_set_preemption_mode(struct nvgpu_channel *ch,
 
 	return err;
 }
+
+u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
+{
+	struct tegra_vgpu_cmd_msg msg = {};
+	struct tegra_vgpu_get_tpc_exception_en_status_params *p =
+				&msg.params.get_tpc_exception_status;
+	u64 tpc_exception_en = 0U;
+	int err = 0;
+
+	msg.cmd = TEGRA_VGPU_CMD_GET_TPC_EXCEPTION_EN_STATUS;
+	msg.handle = vgpu_get_handle(g);
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	err = err ? err : msg.ret;
+	if (err) {
+		nvgpu_err(g,
+			"get tpc enabled exception failed err %d", err);
+		return err;
+	}
+
+	tpc_exception_en = p->tpc_exception_en_sm_mask;
+	return tpc_exception_en;
+}
diff --git a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h
index 6ee62d6b0..7e41670fc 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h
+++ b/drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h
@@ -89,5 +89,6 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
 void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
 			struct tegra_vgpu_sm_esr_info *info);
 int vgpu_init_gr_support(struct gk20a *g);
+u64 vgpu_gr_gk20a_tpc_enabled_exceptions(struct gk20a *g);
 
 #endif /* NVGPU_GR_VGPU_H */
diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
index fd9eaa703..618d62332 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -179,7 +179,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.wait_for_pause = gr_gk20a_wait_for_pause,
 		.resume_from_pause = NULL,
 		.clear_sm_errors = gr_gk20a_clear_sm_errors,
-		.tpc_enabled_exceptions = NULL,
+		.tpc_enabled_exceptions = vgpu_gr_gk20a_tpc_enabled_exceptions,
 		.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
 		.sm_debugger_attached = NULL,
 		.suspend_single_sm = NULL,
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
index b2ad566c5..6c80f403a 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
@@ -2240,9 +2240,10 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g)
 	return ret;
 }
 
-u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
+u64 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g)
 {
-	u32 sm_id, tpc_exception_en = 0;
+	u32 sm_id;
+	u64 tpc_exception_en = 0;
 	u32 offset, regval, tpc_offset, gpc_offset;
 	u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
 	u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h
index 1e25294b4..16b3ff011 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.h
@@ -85,7 +85,7 @@ int gr_gk20a_trigger_suspend(struct gk20a *g);
 int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state);
 int gr_gk20a_resume_from_pause(struct gk20a *g);
 int gr_gk20a_clear_sm_errors(struct gk20a *g);
-u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g);
+u64 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g);
 void gk20a_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
 				u32 *esr_sm_sel);
 void gk20a_gr_init_ovr_sm_dsm_perf(void);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 58639a1df..3e6ec25ce 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -367,7 +367,7 @@ struct gpu_ops {
 		int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state);
 		int (*resume_from_pause)(struct gk20a *g);
 		int (*clear_sm_errors)(struct gk20a *g);
-		u32 (*tpc_enabled_exceptions)(struct gk20a *g);
+		u64 (*tpc_enabled_exceptions)(struct gk20a *g);
 		bool (*sm_debugger_attached)(struct gk20a *g);
 		void (*suspend_single_sm)(struct gk20a *g,
 				u32 gpc, u32 tpc, u32 sm,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
index d75862dfe..538f9efc4 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
@@ -122,6 +122,7 @@ enum {
 	TEGRA_VGPU_CMD_GET_ECC_INFO = 84,
 	TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85,
 	TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK = 86,
+	TEGRA_VGPU_CMD_GET_TPC_EXCEPTION_EN_STATUS = 87,
 };
 
 struct tegra_vgpu_connect_params {
@@ -618,6 +619,10 @@ struct tegra_vgpu_tsg_bind_channel_ex_params {
 	u32 runqueue_sel;
 };
 
+struct tegra_vgpu_get_tpc_exception_en_status_params {
+	u64 tpc_exception_en_sm_mask;
+};
+
 struct tegra_vgpu_cmd_msg {
 	u32 cmd;
 	int ret;
@@ -679,7 +684,8 @@ struct tegra_vgpu_cmd_msg {
 		struct tegra_vgpu_ecc_info_params ecc_info;
 		struct tegra_vgpu_ecc_counter_params ecc_counter;
 		struct tegra_vgpu_set_sm_exception_type_mask_params set_sm_exception_mask;
-		char padding[192];
+		struct tegra_vgpu_get_tpc_exception_en_status_params get_tpc_exception_status;
+		char padding[184];
 	} params;
 };
 
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index 8f357f3f9..2541f804a 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -802,7 +802,7 @@ static int nvgpu_gpu_ioctl_has_any_exception(
 		struct gk20a *g,
 		struct nvgpu_gpu_tpc_exception_en_status_args *args)
 {
-	u32 tpc_exception_en;
+	u64 tpc_exception_en;
 
 	nvgpu_mutex_acquire(&g->dbg_sessions_lock);
 	tpc_exception_en = g->ops.gr.tpc_enabled_exceptions(g);