From 11b34e891facc3ba1b13a08c0e076bbe16bd15d0 Mon Sep 17 00:00:00 2001 From: Abdul Salam Date: Mon, 27 Jan 2020 16:56:45 +0530 Subject: [PATCH] gpu: nvgpu: Refactor Clk unit. As a part of refactoring, need to move clk sw/pmu setup functions from pmu_pstate unit to clk unit as it belongs there. In this patch the public API is moved from pmu_pstate to clk unit and named according to private/public API. NVGPU-4491 Change-Id: I90a7dc821e3a3633c7ac657b398f90e374663d61 Signed-off-by: Abdul Salam Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2282937 Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- arch/nvgpu-common.yaml | 2 + drivers/gpu/nvgpu/common/pmu/clk/clk.c | 151 +++++++++++++++++- drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c | 10 +- drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h | 8 +- drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c | 13 +- drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h | 31 ++++ drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c | 10 +- drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h | 7 +- .../gpu/nvgpu/common/pmu/clk/clk_vf_point.c | 12 +- .../gpu/nvgpu/common/pmu/clk/clk_vf_point.h | 33 ++++ drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c | 12 +- drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h | 7 +- .../gpu/nvgpu/common/pmu/perf/change_seq.c | 2 +- drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c | 2 +- drivers/gpu/nvgpu/common/pmu/pmu_pstate.c | 144 +---------------- drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h | 10 +- .../nvgpu/include/nvgpu/pmu/clk/clk_domain.h | 8 +- .../gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h | 10 +- .../nvgpu/include/nvgpu/pmu/clk/clk_prog.h | 7 +- .../include/nvgpu/pmu/clk/clk_vf_point.h | 6 +- .../gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h | 8 +- 21 files changed, 282 insertions(+), 211 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h create mode 100644 drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml index 1277d11d5..5dfd9008a 100644 --- a/arch/nvgpu-common.yaml +++ b/arch/nvgpu-common.yaml @@ -780,6 +780,7 @@ pmu: safe: yes gpu: dgpu sources: [ common/pmu/clk/clk_fll.c, + common/pmu/clk/clk_fll.h, include/nvgpu/pmu/clk/clk_fll.h ] prog: @@ -793,6 +794,7 @@ pmu: safe: yes gpu: dgpu sources: [ common/pmu/clk/clk_vf_point.c, + common/pmu/clk/clk_vf_point.h, include/nvgpu/pmu/clk/clk_vf_point.h ] vin: safe: yes diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c index 848594381..3f162b132 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c @@ -35,7 +35,13 @@ #include #include -int nvgpu_clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx, +#include "clk_domain.h" +#include "clk_prog.h" +#include "clk_vin.h" +#include "clk_fll.h" +#include "clk_vf_point.h" + +int nvgpu_pmu_clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx, u32 *pclkmhz, u32 *pvoltuv, u8 railidx) { @@ -68,7 +74,7 @@ int nvgpu_clk_get_fll_clks(struct gk20a *g, } #endif -int nvgpu_clk_init_pmupstate(struct gk20a *g) +int clk_init_pmupstate(struct gk20a *g) { /* If already allocated, do not re-allocate */ if (g->pmu->clk_pmu != NULL) { @@ -83,7 +89,7 @@ int nvgpu_clk_init_pmupstate(struct gk20a *g) return 0; } -void nvgpu_clk_free_pmupstate(struct gk20a *g) +void clk_free_pmupstate(struct gk20a *g) { nvgpu_kfree(g, g->pmu->clk_pmu); g->pmu->clk_pmu = NULL; @@ -107,3 +113,142 @@ u32 nvgpu_clk_mon_init_domains(struct gk20a *g) CTRL_CLK_DOMAIN_PEX_REFCLK ); return domain_mask; } + +int nvgpu_pmu_clk_pmu_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = clk_domain_pmu_setup(g); + if (err != 0) { + return err; + } + + err = clk_prog_pmu_setup(g); + if (err != 0) { + return err; + } + + err = clk_vin_pmu_setup(g); + if (err != 0) { + return err; + } + + err = clk_fll_pmu_setup(g); + if (err != 0) { + return err; + } + + if (g->ops.clk.support_vf_point) { + err = clk_vf_point_pmu_setup(g); + if (err != 0) { + return err; + } + } + + err = clk_pmu_vin_load(g); + if (err != 0) { + return err; + } + + err = clk_pmu_clk_domains_load(g); + if (err != 0) { + return err; + } + + return 0; +} + +int nvgpu_pmu_clk_sw_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = clk_vin_sw_setup(g); + if (err != 0) { + clk_vin_free_pmupstate(g); + return err; + } + + err = clk_fll_sw_setup(g); + if (err != 0) { + clk_fll_free_pmupstate(g); + return err; + } + + err = clk_domain_sw_setup(g); + if (err != 0) { + clk_domain_free_pmupstate(g); + return err; + } + + if (g->ops.clk.support_vf_point) { + err = clk_vf_point_sw_setup(g); + if (err != 0) { + clk_vf_point_free_pmupstate(g); + return err; + } + } + + err = clk_prog_sw_setup(g); + if (err != 0) { + clk_prog_free_pmupstate(g); + return err; + } + + return 0; +} +int nvgpu_pmu_clk_init(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = clk_init_pmupstate(g); + if (err != 0) { + clk_free_pmupstate(g); + return err; + } + + err = clk_domain_init_pmupstate(g); + if (err != 0) { + clk_domain_free_pmupstate(g); + return err; + } + + err = clk_prog_init_pmupstate(g); + if (err != 0) { + clk_prog_free_pmupstate(g); + return err; + } + + err = clk_vf_point_init_pmupstate(g); + if (err != 0) { + clk_vf_point_free_pmupstate(g); + return err; + } + + err = clk_vin_init_pmupstate(g); + if (err != 0) { + clk_vin_free_pmupstate(g); + return err; + } + + err = clk_fll_init_pmupstate(g); + if (err != 0) { + clk_fll_free_pmupstate(g); + return err; + } + + return 0; +} +void nvgpu_pmu_clk_deinit(struct gk20a *g) +{ + if ((g->pmu != NULL) && (g->pmu->clk_pmu != NULL)) { + clk_domain_free_pmupstate(g); + clk_prog_free_pmupstate(g); + clk_vf_point_free_pmupstate(g); + clk_fll_free_pmupstate(g); + clk_vin_free_pmupstate(g); + clk_free_pmupstate(g); + } +} diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c index cdc80f08f..e6c40a47e 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c @@ -213,7 +213,7 @@ static int _clk_domains_pmudata_instget(struct gk20a *g, return 0; } -int nvgpu_clk_domain_sw_setup(struct gk20a *g) +int clk_domain_sw_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -370,7 +370,7 @@ done: return status; } -int nvgpu_clk_domain_pmu_setup(struct gk20a *g) +int clk_domain_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -1380,7 +1380,7 @@ done: return status; } -int nvgpu_clk_pmu_clk_domains_load(struct gk20a *g) +int clk_pmu_clk_domains_load(struct gk20a *g) { int status; struct nvgpu_pmu *pmu = g->pmu; @@ -1620,7 +1620,7 @@ static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain, } #endif -int nvgpu_clk_domain_init_pmupstate(struct gk20a *g) +int clk_domain_init_pmupstate(struct gk20a *g) { /* If already allocated, do not re-allocate */ if (g->pmu->clk_pmu->clk_domainobjs != NULL) { @@ -1647,7 +1647,7 @@ int nvgpu_clk_domain_init_pmupstate(struct gk20a *g) return 0; } -void nvgpu_clk_domain_free_pmupstate(struct gk20a *g) +void clk_domain_free_pmupstate(struct gk20a *g) { nvgpu_kfree(g, g->pmu->clk_pmu->clk_domainobjs); g->pmu->clk_pmu->clk_domainobjs = NULL; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h index b3a0b7582..72fe1f60c 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -104,4 +104,10 @@ struct clk_domain_35_slave { struct clk_domain_30_slave slave; }; +int clk_domain_init_pmupstate(struct gk20a *g); +void clk_domain_free_pmupstate(struct gk20a *g); +int clk_pmu_clk_domains_load(struct gk20a *g); +int clk_domain_sw_setup(struct gk20a *g); +int clk_domain_pmu_setup(struct gk20a *g); + #endif /* NVGPU_CLK_DOMAIN_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c index 55e8724df..7ed560816 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,6 +33,7 @@ #include #include +#include "clk_fll.h" #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10U #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK 0x1FU @@ -136,7 +137,7 @@ static int _clk_fll_devgrp_pmustatus_instget(struct gk20a *g, return 0; } -int nvgpu_clk_fll_sw_setup(struct gk20a *g) +int clk_fll_sw_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -237,7 +238,7 @@ done: return status; } -int nvgpu_clk_fll_pmu_setup(struct gk20a *g) +int clk_fll_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -596,7 +597,7 @@ static int get_regime_id(struct gk20a *g, u32 domain, u8 *regimeid) return -EINVAL; } -u8 nvgpu_clk_fll_get_fmargin_idx(struct gk20a *g) +u8 nvgpu_pmu_clk_fll_get_fmargin_idx(struct gk20a *g) { struct nvgpu_avfsfllobjs *pfllobjs = g->pmu->clk_pmu->avfs_fllobjs; u8 fmargin_idx; @@ -608,7 +609,7 @@ u8 nvgpu_clk_fll_get_fmargin_idx(struct gk20a *g) return fmargin_idx; } -int nvgpu_clk_fll_init_pmupstate(struct gk20a *g) +int clk_fll_init_pmupstate(struct gk20a *g) { /* If already allocated, do not re-allocate */ if (g->pmu->clk_pmu->avfs_fllobjs != NULL) { @@ -634,7 +635,7 @@ int nvgpu_clk_fll_init_pmupstate(struct gk20a *g) return 0; } -void nvgpu_clk_fll_free_pmupstate(struct gk20a *g) +void clk_fll_free_pmupstate(struct gk20a *g) { nvgpu_kfree(g, g->pmu->clk_pmu->avfs_fllobjs); g->pmu->clk_pmu->avfs_fllobjs = NULL; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h new file mode 100644 index 000000000..e1bc1ab69 --- /dev/null +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_fll.h @@ -0,0 +1,31 @@ +/* + * general clock structures & definitions + * + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_CLK_FLL_H +#define NVGPU_CLK_FLL_H + +int clk_fll_init_pmupstate(struct gk20a *g); +void clk_fll_free_pmupstate(struct gk20a *g); +int clk_fll_sw_setup(struct gk20a *g); +int clk_fll_pmu_setup(struct gk20a *g); +#endif /* NVGPU_CLK_FLL_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c index 400edb9ea..0bf76a094 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -110,7 +110,7 @@ static int _clk_progs_pmudata_instget(struct gk20a *g, return 0; } -int nvgpu_clk_prog_sw_setup(struct gk20a *g) +int clk_prog_sw_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -161,7 +161,7 @@ done: return status; } -int nvgpu_clk_prog_pmu_setup(struct gk20a *g) +int clk_prog_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -1372,7 +1372,7 @@ static int getslaveclk_prog_1x_master(struct gk20a *g, return 0; } -int nvgpu_clk_prog_init_pmupstate(struct gk20a *g) +int clk_prog_init_pmupstate(struct gk20a *g) { /* If already allocated, do not re-allocate */ if (g->pmu->clk_pmu->clk_progobjs != NULL) { @@ -1388,7 +1388,7 @@ int nvgpu_clk_prog_init_pmupstate(struct gk20a *g) return 0; } -void nvgpu_clk_prog_free_pmupstate(struct gk20a *g) +void clk_prog_free_pmupstate(struct gk20a *g) { nvgpu_kfree(g, g->pmu->clk_pmu->clk_progobjs); g->pmu->clk_pmu->clk_progobjs = NULL; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h index 382608966..37969d048 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -127,4 +127,9 @@ struct clk_prog_35_master_table { ((struct clk_prog *)(void *)BOARDOBJGRP_OBJ_GET_BY_IDX(\ &pclk->clk_progobjs->super.super, (u8)(idx))) + +int clk_prog_init_pmupstate(struct gk20a *g); +void clk_prog_free_pmupstate(struct gk20a *g); +int clk_prog_sw_setup(struct gk20a *g); +int clk_prog_pmu_setup(struct gk20a *g); #endif /* NVGPU_CLK_PROG_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c index 100071d7e..44cc905d5 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,6 +37,8 @@ #include #include +#include "clk_vf_point.h" + int nvgpu_clk_domain_volt_to_freq(struct gk20a *g, u8 clkdomain_idx, u32 *pclkmhz, u32 *pvoltuv, u8 railidx) { @@ -122,7 +124,7 @@ static int _clk_vf_points_pmustatus_instget(struct gk20a *g, return 0; } -int nvgpu_clk_vf_point_sw_setup(struct gk20a *g) +int clk_vf_point_sw_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -170,7 +172,7 @@ done: return status; } -int nvgpu_clk_vf_point_pmu_setup(struct gk20a *g) +int clk_vf_point_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -483,7 +485,7 @@ int nvgpu_clk_vf_point_cache(struct gk20a *g) } #endif -int nvgpu_clk_vf_point_init_pmupstate(struct gk20a *g) +int clk_vf_point_init_pmupstate(struct gk20a *g) { /* If already allocated, do not re-allocate */ if (g->pmu->clk_pmu->clk_vf_pointobjs != NULL) { @@ -501,7 +503,7 @@ int nvgpu_clk_vf_point_init_pmupstate(struct gk20a *g) return 0; } -void nvgpu_clk_vf_point_free_pmupstate(struct gk20a *g) +void clk_vf_point_free_pmupstate(struct gk20a *g) { nvgpu_kfree(g, g->pmu->clk_pmu->clk_vf_pointobjs); g->pmu->clk_pmu->clk_vf_pointobjs = NULL; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h new file mode 100644 index 000000000..a5c846ed2 --- /dev/null +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.h @@ -0,0 +1,33 @@ +/* + * general clock structures & definitions + * + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_CLK_VF_POINT_H +#define NVGPU_CLK_VF_POINT_H + +int clk_vf_point_init_pmupstate(struct gk20a *g); +void clk_vf_point_free_pmupstate(struct gk20a *g); +int clk_vf_point_sw_setup(struct gk20a *g); +int clk_vf_point_pmu_setup(struct gk20a *g); + +#endif /* NVGPU_CLK_VF_POINT_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c index 6a429ddea..14966368b 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -155,7 +155,7 @@ static int _clk_vin_devgrp_pmustatus_instget(struct gk20a *g, return 0; } -int nvgpu_clk_vin_sw_setup(struct gk20a *g) +int clk_vin_sw_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -219,7 +219,7 @@ done: return status; } -int nvgpu_clk_vin_pmu_setup(struct gk20a *g) +int clk_vin_pmu_setup(struct gk20a *g) { int status; struct boardobjgrp *pboardobjgrp = NULL; @@ -479,7 +479,7 @@ static int vin_device_init_pmudata_super(struct gk20a *g, return status; } -int nvgpu_clk_pmu_vin_load(struct gk20a *g) +int clk_pmu_vin_load(struct gk20a *g) { int status; struct nvgpu_pmu *pmu = g->pmu; @@ -503,7 +503,7 @@ int nvgpu_clk_pmu_vin_load(struct gk20a *g) return status; } -int nvgpu_clk_vin_init_pmupstate(struct gk20a *g) +int clk_vin_init_pmupstate(struct gk20a *g) { /* If already allocated, do not re-allocate */ if (g->pmu->clk_pmu->avfs_vinobjs != NULL) { @@ -521,7 +521,7 @@ int nvgpu_clk_vin_init_pmupstate(struct gk20a *g) return 0; } -void nvgpu_clk_vin_free_pmupstate(struct gk20a *g) +void clk_vin_free_pmupstate(struct gk20a *g) { nvgpu_kfree(g, g->pmu->clk_pmu->avfs_vinobjs); g->pmu->clk_pmu->avfs_vinobjs = NULL; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h index aa39b3524..f1bd97a42 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,4 +33,9 @@ struct vin_device_v20 { struct ctrl_clk_vin_device_info_data_v20 data; }; +int clk_vin_init_pmupstate(struct gk20a *g); +void clk_vin_free_pmupstate(struct gk20a *g); +int clk_pmu_vin_load(struct gk20a *g); +int clk_vin_sw_setup(struct gk20a *g); +int clk_vin_pmu_setup(struct gk20a *g); #endif /* NVGPU_CLK_VIN_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c index 757914172..69dfb3591 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c @@ -288,7 +288,7 @@ int nvgpu_pmu_perf_changeseq_set_clks(struct gk20a *g, } gpcclk_clkmhz += fmargin_mhz; - status = nvgpu_clk_domain_freq_to_volt(g, gpcclk_domain, + status = nvgpu_pmu_clk_domain_freq_to_volt(g, gpcclk_domain, &gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); status = nvgpu_pmu_perf_vfe_get_volt_margin(g, &vmargin_uv); diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c index 49e25bc79..b198e2a68 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c @@ -945,7 +945,7 @@ int nvgpu_pmu_perf_vfe_get_freq_margin(struct gk20a *g, u32 *fmargin_mhz) int status = 0; u8 fmargin_idx; - fmargin_idx = nvgpu_clk_fll_get_fmargin_idx(g); + fmargin_idx = nvgpu_pmu_clk_fll_get_fmargin_idx(g); if (fmargin_idx == 0U) { return 0; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c index f3277a409..5f858ab15 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c @@ -50,64 +50,13 @@ void nvgpu_pmu_pstate_deinit(struct gk20a *g) nvgpu_pmu_perf_deinit(g); } - if (g->pmu->clk_pmu != NULL) { - nvgpu_clk_domain_free_pmupstate(g); - nvgpu_clk_prog_free_pmupstate(g); - nvgpu_clk_vf_point_free_pmupstate(g); - nvgpu_clk_fll_free_pmupstate(g); - nvgpu_clk_vin_free_pmupstate(g); - nvgpu_clk_free_pmupstate(g); - } + nvgpu_pmu_clk_deinit(g); if (g->ops.clk.mclk_deinit != NULL) { g->ops.clk.mclk_deinit(g); } } -static int pmu_pstate_clk_init(struct gk20a *g) -{ - int err; - nvgpu_log_fn(g, " "); - - err = nvgpu_clk_init_pmupstate(g); - if (err != 0) { - nvgpu_clk_free_pmupstate(g); - return err; - } - - err = nvgpu_clk_domain_init_pmupstate(g); - if (err != 0) { - nvgpu_clk_domain_free_pmupstate(g); - return err; - } - - err = nvgpu_clk_prog_init_pmupstate(g); - if (err != 0) { - nvgpu_clk_prog_free_pmupstate(g); - return err; - } - - err = nvgpu_clk_vf_point_init_pmupstate(g); - if (err != 0) { - nvgpu_clk_vf_point_free_pmupstate(g); - return err; - } - - err = nvgpu_clk_vin_init_pmupstate(g); - if (err != 0) { - nvgpu_clk_vin_free_pmupstate(g); - return err; - } - - err = nvgpu_clk_fll_init_pmupstate(g); - if (err != 0) { - nvgpu_clk_fll_free_pmupstate(g); - return err; - } - - return 0; -} - static int pmu_pstate_init(struct gk20a *g) { int err; @@ -119,7 +68,7 @@ static int pmu_pstate_init(struct gk20a *g) return err; } - err = pmu_pstate_clk_init(g); + err = nvgpu_pmu_clk_init(g); if (err != 0) { return err; } @@ -139,46 +88,6 @@ static int pmu_pstate_init(struct gk20a *g) return 0; } -static int pmu_pstate_clk_sw_setup(struct gk20a *g) -{ - int err; - nvgpu_log_fn(g, " "); - - err = nvgpu_clk_vin_sw_setup(g); - if (err != 0) { - nvgpu_clk_vin_free_pmupstate(g); - return err; - } - - err = nvgpu_clk_fll_sw_setup(g); - if (err != 0) { - nvgpu_clk_fll_free_pmupstate(g); - return err; - } - - err = nvgpu_clk_domain_sw_setup(g); - if (err != 0) { - nvgpu_clk_domain_free_pmupstate(g); - return err; - } - - if (g->ops.clk.support_vf_point) { - err = nvgpu_clk_vf_point_sw_setup(g); - if (err != 0) { - nvgpu_clk_vf_point_free_pmupstate(g); - return err; - } - } - - err = nvgpu_clk_prog_sw_setup(g); - if (err != 0) { - nvgpu_clk_prog_free_pmupstate(g); - return err; - } - - return 0; -} - /*sw setup for pstate components*/ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g) { @@ -208,7 +117,7 @@ int nvgpu_pmu_pstate_sw_setup(struct gk20a *g) goto err_therm_pmu_init_pmupstate; } - err = pmu_pstate_clk_sw_setup(g); + err = nvgpu_pmu_clk_sw_setup(g); if (err != 0) { nvgpu_err(g, "Clk sw setup failed"); return err; @@ -239,51 +148,6 @@ err_perf_pmu_init_pmupstate: return err; } -static int pmu_pstate_clk_pmu_setup(struct gk20a *g) -{ - int err; - nvgpu_log_fn(g, " "); - - err = nvgpu_clk_domain_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_prog_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_vin_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_fll_pmu_setup(g); - if (err != 0) { - return err; - } - - if (g->ops.clk.support_vf_point) { - err = nvgpu_clk_vf_point_pmu_setup(g); - if (err != 0) { - return err; - } - } - - err = nvgpu_clk_pmu_vin_load(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_pmu_clk_domains_load(g); - if (err != 0) { - return err; - } - - return 0; -} - /*sw setup for pstate components*/ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g) { @@ -309,7 +173,7 @@ int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g) return err; } - err = pmu_pstate_clk_pmu_setup(g); + err = nvgpu_pmu_clk_pmu_setup(g); if (err != 0) { nvgpu_err(g, "Failed to send CLK pmu setup"); return err; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h index 3fed73898..af40786e8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h @@ -95,13 +95,17 @@ struct nvgpu_clk_pmupstate { int (*nvgpu_clk_vf_point_cache)(struct gk20a *g); }; -int nvgpu_clk_init_pmupstate(struct gk20a *g); -void nvgpu_clk_free_pmupstate(struct gk20a *g); +int clk_init_pmupstate(struct gk20a *g); +void clk_free_pmupstate(struct gk20a *g); int nvgpu_clk_get_fll_clks(struct gk20a *g, struct nvgpu_set_fll_clk *setfllclk); -int nvgpu_clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx, +int nvgpu_pmu_clk_domain_freq_to_volt(struct gk20a *g, u8 clkdomain_idx, u32 *pclkmhz, u32 *pvoltuv, u8 railidx); int nvgpu_clk_domain_get_from_index(struct gk20a *g, u32 *domain, u32 index); u32 nvgpu_clk_mon_init_domains(struct gk20a *g); +int nvgpu_pmu_clk_pmu_setup(struct gk20a *g); +int nvgpu_pmu_clk_sw_setup(struct gk20a *g); +int nvgpu_pmu_clk_init(struct gk20a *g); +void nvgpu_pmu_clk_deinit(struct gk20a *g); #endif /* NVGPU_PMU_CLK_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h index 96dc61873..5bb452b2c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h @@ -1,7 +1,7 @@ /* * general clock structures & definitions * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -80,10 +80,4 @@ struct nvgpu_clk_domains { *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS]; }; -int nvgpu_clk_domain_init_pmupstate(struct gk20a *g); -void nvgpu_clk_domain_free_pmupstate(struct gk20a *g); -int nvgpu_clk_pmu_clk_domains_load(struct gk20a *g); -int nvgpu_clk_domain_sw_setup(struct gk20a *g); -int nvgpu_clk_domain_pmu_setup(struct gk20a *g); - #endif /* NVGPU_PMU_CLK_DOMAIN_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h index dcd570ac8..2a2ed9b8f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h @@ -1,7 +1,7 @@ /* * general clock structures & definitions * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -67,12 +67,6 @@ struct fll_device { struct boardobjgrpmask_e32 lut_prog_broadcast_slave_mask; fll_lut_broadcast_slave_register *lut_broadcast_slave_register; }; - - -int nvgpu_clk_fll_init_pmupstate(struct gk20a *g); -void nvgpu_clk_fll_free_pmupstate(struct gk20a *g); -int nvgpu_clk_fll_sw_setup(struct gk20a *g); -int nvgpu_clk_fll_pmu_setup(struct gk20a *g); -u8 nvgpu_clk_fll_get_fmargin_idx(struct gk20a *g); +u8 nvgpu_pmu_clk_fll_get_fmargin_idx(struct gk20a *g); #endif /* NVGPU_PMU_CLK_FLL_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_prog.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_prog.h index faa9842b5..57f395d44 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_prog.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_prog.h @@ -1,7 +1,7 @@ /* * general clock structures & definitions * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -38,9 +38,4 @@ struct nvgpu_clk_progs { u8 vf_sec_entry_count; }; -int nvgpu_clk_prog_init_pmupstate(struct gk20a *g); -void nvgpu_clk_prog_free_pmupstate(struct gk20a *g); -int nvgpu_clk_prog_sw_setup(struct gk20a *g); -int nvgpu_clk_prog_pmu_setup(struct gk20a *g); - #endif /* NVGPU_PMU_CLK_PROG_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h index fc384c46d..149205bc6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h @@ -1,7 +1,7 @@ /* * general clock structures & definitions * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -84,10 +84,6 @@ struct clk_vf_point_freq { #define clkvfpointvoltageuvget(pgpu, pvfpoint) \ CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(clkvfpointpairget(pvfpoint)) \ -int nvgpu_clk_vf_point_init_pmupstate(struct gk20a *g); -void nvgpu_clk_vf_point_free_pmupstate(struct gk20a *g); -int nvgpu_clk_vf_point_sw_setup(struct gk20a *g); -int nvgpu_clk_vf_point_pmu_setup(struct gk20a *g); struct clk_vf_point *nvgpu_construct_clk_vf_point(struct gk20a *g, void *pargs); int nvgpu_clk_arb_find_slave_points(struct nvgpu_clk_arb *arb, diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h index 3d030cd86..0dcc723cf 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h @@ -1,7 +1,7 @@ /* * general clock structures & definitions * - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -56,10 +56,4 @@ struct nvgpu_avfsvinobjs { bool vin_is_disable_allowed; }; -int nvgpu_clk_vin_init_pmupstate(struct gk20a *g); -void nvgpu_clk_vin_free_pmupstate(struct gk20a *g); -int nvgpu_clk_pmu_vin_load(struct gk20a *g); -int nvgpu_clk_vin_sw_setup(struct gk20a *g); -int nvgpu_clk_vin_pmu_setup(struct gk20a *g); - #endif /* NVGPU_PMU_CLK_VIN_H */