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gpu: nvgpu: Rename struct nvgpu_runlist_info, fields in fifo

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Rename struct nvgpu_runlist_info to struct nvgpu_runlist; the
info is not necessary. struct nvgpu_runlist is soon to be a
first class object among the nvgpu object model.

Also rename the fields runlist_info and active_runlist_info to
simply runlists and active_runlists respectively. Again the info
text is just not necessary and somewhat misleading. These structs
_are_ the runlist representations in SW; they are not merely
informational.

Also add an rl_dbg() macro to print debug info specific to
runlist management and some debug prints specifying the runlist
topology for the running chip.

Change-Id: Id9fcbdd1a7227cb5f8c75cca4abbff94fe048e49
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2470303
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2020-12-31 19:40:00 -06:00
committed by mobile promotions
parent a4dc48061c
commit 11d3785faf
18 changed files with 137 additions and 127 deletions
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14
drivers/gpu/nvgpu/include/nvgpu/fifo.h
View File

@@ -1,7 +1,7 @@
/*
* FIFO common definitions.
*
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -131,7 +131,7 @@
*
* TODO
*
* + struct nvgpu_runlist_info
* + struct nvgpu_runlist
*
* TODO
*
@@ -225,7 +225,7 @@
#define CHANNEL_INFO_VEID0 0U
struct gk20a;
struct nvgpu_runlist_info;
struct nvgpu_runlist;
struct nvgpu_channel;
struct nvgpu_tsg;
struct nvgpu_swprofiler;
@@ -277,15 +277,15 @@ struct nvgpu_fifo {
/**
* Pointers to runlists, indexed by real hw runlist_id.
* If a runlist is active, then runlist_info[runlist_id] points
* If a runlist is active, then runlists[runlist_id] points
* to one entry in active_runlist_info. Otherwise, it is NULL.
*/
struct nvgpu_runlist_info **runlist_info;
struct nvgpu_runlist **runlists;
/** Number of runlists supported by the h/w. */
u32 max_runlists;
/** Array of runlists that are actually in use. */
struct nvgpu_runlist_info *active_runlist_info;
/** Array of actual HW runlists that are present on the GPU. */
struct nvgpu_runlist *active_runlists;
/** Number of active runlists. */
u32 num_runlists;

3
drivers/gpu/nvgpu/include/nvgpu/log_common.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -74,5 +74,6 @@ enum nvgpu_log_type {
#define gpu_dbg_mig BIT(33) /* MIG info */
#define gpu_dbg_rec BIT(34) /* Recovery sequence debugging. */
#define gpu_dbg_zbc BIT(35) /* Gr ZBC */
#define gpu_dbg_runlists BIT(38) /* Runlist related debugging. */
#endif

12
drivers/gpu/nvgpu/include/nvgpu/runlist.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -79,7 +79,7 @@ struct nvgpu_channel;
/** Runlist identifier is invalid. */
#define NVGPU_INVALID_RUNLIST_ID U32_MAX
struct nvgpu_runlist_info {
struct nvgpu_runlist {
/** Runlist identifier. */
u32 runlist_id;
/** Bitmap of active channels in the runlist. One bit per chid. */
@@ -104,7 +104,7 @@ struct nvgpu_runlist_info {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
/* nvgpu next runlist info additions */
struct nvgpu_next_runlist_info nvgpu_next;
struct nvgpu_next_runlist nvgpu_next;
#endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
};
@@ -128,7 +128,7 @@ struct nvgpu_runlist_info {
* runlist buffer to describe all active channels and TSGs.
*/
u32 nvgpu_runlist_construct_locked(struct nvgpu_fifo *f,
struct nvgpu_runlist_info *runlist,
struct nvgpu_runlist *runlist,
u32 buf_id, u32 max_entries);
/**
@@ -365,4 +365,8 @@ u32 nvgpu_runlist_get_runlists_mask(struct gk20a *g, u32 id,
*/
void nvgpu_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f);
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
#define rl_dbg(g, fmt, arg...) \
nvgpu_log(g, gpu_dbg_runlists, "RL | " fmt, ##arg)
#endif /* NVGPU_RUNLIST_H */