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gpu: nvgpu: Fix white space in enabled.h

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Clean up the tabbing to make all enabled flags have similar tab
offsets.

JIRA NVGPU-1737
JIRA NVGPU-1029

Change-Id: Ib647b0d1a0f2d9d8e0096de7dcbc6db1e2d45c10
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989499
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2019-01-07 12:31:46 -08:00
committed by mobile promotions
parent 489236d181
commit 11e9e8fa49
1 changed files with 10 additions and 10 deletions
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20
drivers/gpu/nvgpu/include/nvgpu/enabled.h
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@@ -33,7 +33,7 @@ struct gk20a;
*/ */
#define NVGPU_IS_FMODEL 1 #define NVGPU_IS_FMODEL 1
#define NVGPU_DRIVER_IS_DYING 2 #define NVGPU_DRIVER_IS_DYING 2
#define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3 #define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3
#define NVGPU_FECS_TRACE_VA 4 #define NVGPU_FECS_TRACE_VA 4
#define NVGPU_CAN_RAILGATE 5 #define NVGPU_CAN_RAILGATE 5
#define NVGPU_KERNEL_IS_DYING 6 #define NVGPU_KERNEL_IS_DYING 6
@@ -130,13 +130,13 @@ struct gk20a;
* PMU flags. * PMU flags.
*/ */
/* perfmon enabled or disabled for PMU */ /* perfmon enabled or disabled for PMU */
#define NVGPU_PMU_PERFMON 48 #define NVGPU_PMU_PERFMON 48
#define NVGPU_PMU_PSTATE 49 #define NVGPU_PMU_PSTATE 49
#define NVGPU_PMU_ZBC_SAVE 50 #define NVGPU_PMU_ZBC_SAVE 50
#define NVGPU_PMU_FECS_BOOTSTRAP_DONE 51 #define NVGPU_PMU_FECS_BOOTSTRAP_DONE 51
#define NVGPU_GPU_CAN_BLCG 52 #define NVGPU_GPU_CAN_BLCG 52
#define NVGPU_GPU_CAN_SLCG 53 #define NVGPU_GPU_CAN_SLCG 53
#define NVGPU_GPU_CAN_ELCG 54 #define NVGPU_GPU_CAN_ELCG 54
/* Clock control support */ /* Clock control support */
#define NVGPU_SUPPORT_CLOCK_CONTROLS 55 #define NVGPU_SUPPORT_CLOCK_CONTROLS 55
/* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */ /* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */
@@ -169,10 +169,10 @@ struct gk20a;
#define NVGPU_SUPPORT_USERMODE_SUBMIT 67 #define NVGPU_SUPPORT_USERMODE_SUBMIT 67
/* Multiple WPR support */ /* Multiple WPR support */
#define NVGPU_SUPPORT_MULTIPLE_WPR 68 #define NVGPU_SUPPORT_MULTIPLE_WPR 68
/* SEC2 RTOS support*/ /* SEC2 RTOS support*/
#define NVGPU_SUPPORT_SEC2_RTOS 69 #define NVGPU_SUPPORT_SEC2_RTOS 69
/* /*
* Must be greater than the largest bit offset in the above list. * Must be greater than the largest bit offset in the above list.