From 120f9e40a31f7fc9ee292c3f53134e403404c5de Mon Sep 17 00:00:00 2001 From: Divya Date: Tue, 17 Jan 2023 13:43:07 +0000 Subject: [PATCH] gpu: nvgpu: Add NULL checks for therm HALs Add NULL checks for therm HALs JIRA NVGPU-9495 Change-Id: If4fd1166c11070a978546e701157d2a217008e39 Signed-off-by: Divya Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2844938 Reviewed-by: Seema Khowala Reviewed-by: Rajesh Devaraj Reviewed-by: svcacv Tested-by: Rajesh Devaraj GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/power_features/cg/cg.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/power_features/cg/cg.c b/drivers/gpu/nvgpu/common/power_features/cg/cg.c index fba7ca2db..6af384f46 100644 --- a/drivers/gpu/nvgpu/common/power_features/cg/cg.c +++ b/drivers/gpu/nvgpu/common/power_features/cg/cg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,6 +33,11 @@ static void nvgpu_cg_set_mode(struct gk20a *g, u32 cgmode, u32 mode_config) const struct nvgpu_device *dev = NULL; struct nvgpu_fifo *f = &g->fifo; + if ((g->ops.therm.init_blcg_mode == NULL) && + (g->ops.therm.init_elcg_mode == NULL)) { + return; + } + nvgpu_log_fn(g, " "); for (n = 0; n < f->num_engines; n++) { @@ -41,7 +46,7 @@ static void nvgpu_cg_set_mode(struct gk20a *g, u32 cgmode, u32 mode_config) #ifdef CONFIG_NVGPU_NON_FUSA /* gr_engine supports both BLCG and ELCG */ if ((cgmode == BLCG_MODE) && - (dev->type == NVGPU_DEVTYPE_GRAPHICS)) { + (dev->type == NVGPU_DEVTYPE_GRAPHICS)) { g->ops.therm.init_blcg_mode(g, (u32)mode_config, engine_id); break;